An Overview of Analog Feedback Part II: Amplifier Configurations in Generic Device Technologies

In this second installment of a two part paper that overviews analog feedback circuits, computationally efficient and general feedback analysis techniques applicable to virtually all three and four terminal device technologies are formulated. As developed in Part I, these techniques coalesce signal flow and two port network theories in a way that clearly illuminates the loop gain, driving point I/O impedances, and other characteristics of any type of feedback configuration. More than simply developing the signal flow-two port methodology, this paper demonstrates its design-oriented utility by applying the new technique to the problem of assessing the performance attributes and limitations of four single loop and two dual loop feedback architectures.Three advantages are gleaned by the signal flow-two port method of feedback network analysis. The first advantage is its amenability to a straightforward application of the stability theories and compensation strategies discussed in Part I. The second is its ability to underscore the magnitude of potentially troublesome feedforward factors associated with the feedback network. Once the extent of this parasitic feedforward is highlighted, the topological nature of appropriate feedforward compensation is relatively easy to innovate. The third advantage of signal flow-two port analytical methods is its ability to simplify the analysis of dual loop feedback architectures. This last advantage is noteworthy in view of the fact that dual feedback loops offer the only practical analog mechanism for desensitizing the gain and I/O impedances with respect to uncertainties in open loop parameters.     

Exploiting the high-frequency performance of low-voltage low-power SC filters

This paper investigates the design of low-voltage low-power switched-capacitor (SC) filters for high-frequency applications by using the clock-booster approach. In particular, our proposed SC filter architecture uses single-ended double-sampling integrator cells based on low-voltage operational transconductance amplifiers which take advantage of dynamic biasing and the clock-booster technique to drive the switch transistors. To validate its high-frequency capability, two low-pass elliptic SC filters respectively with a corner frequency of 6 and 8-MHz, were designed in a 0.35-/spl mu/m CMOS process. Both are suitable for telecom applications and can operate with a power supply as low as 1.5 V, while dissipating 11 mW. Measurements showed that for an output amplitude of 1 V/sub pp/, their total harmonic distortions were maintained well below -40 dB in their bandwidths. Comparisons with other SC filter implementations in the literature, which highlight the quality of our implementation are also provided.     

Optimised design of ECL gates with power constraint

A design strategy for the optimisation of the propagation delay of low-power emitter coupled logic gates is discussed. These results can be applied when there is a power constraint and the level of available current is lower than the optimum. The strategy is independent of the process used and simple to design, avoiding the trial-and-error approach based on simulations. The use of the procedure is illustrated and validated by SPICE simulations on a two input multiplexer, using a bipolar process the npn transistor of which has an f/sub T/ of 20 GHz.     

Low-power high-speed rail-to-rail LCD output buffer with dual-path push–pull operation and quiescent current control

The present paper addresses a new compact low-power high-speed output buffer amplifier topology for large-size liquid crystal display applications. The suggested buffer achieves fast driving performance, draws a low quiescent current during static operation and offers a rail-to-rail common-mode input range. The circuit provides enhanced slewing capabilities with a limited power consumption by simultaneously exploiting the push–pull output sections of two basic complementary-type input amplifiers to realize a dual-path push–pull operation of the output stage. An auxiliary biasing network integrated in the input differential stage allows the quiescent bias conditions of the class-AB output stage to be inherently controlled without additional current dissipation. Post-layout simulation results confirm that the proposed amplifier can drive a 1-nF column line load within a 0.9-μs settling time under a 3-V full voltage swing, while drawing only 3.5-μA quiescent current. Monte Carlo simulations are finally carried out, showing a good degree of robustness of the proposed output buffer against process and mismatch variations.     

Gain-compensated sample-and-hold circuit for high frequency application

A novel and fast and accurate sample-and-hold circuit is presented which can be designed using conventional single stage amplifiers. The offset contribution to the output voltage is intrinsically compensated and the clock-feedthrough error can be reduced by slightly changing the clock phase scheme.<>     

Postal address reading in real time

In 1994, the U.S. Postal Service (USPS) delivered 177 billion pieces of mail to 125 million delivery addresses. To assist in processing this large volume of mail, USPS and the Center for Document Analysis and Recognition (CEDAR) have been exploring automation methods for processing letter mail with handwritten addresses. The CEDAR system for locating and reading destination address blocks on letter mail pieces operates at real-time rates. The system architecture uses a variety of pipelining and multiprocessor techniques to achieve the required processing speed and minimize latency. Image processing operations are performed using specialized hardware operating at 103 ns/pixel. This hardware includes CCITT Group 3 (FAX) decompression, image enhancement, and conversion of the image representation from pixel-based representation to symbolic representation. This symbolic representation of the image can be processed in real time using software running on general-purpose processors. This software performs the address block location (ABL), handwritten address interpretation (HWAI), and data base querying needed to determine the delivery point of the mail piece. The current system can correctly locate and produce a five-digit ZIP code with an accuracy of 66% on a test set of 1566 handwritten mail pieces. A unique delivery point (e.g., ZIP + 4 code) can be determined on these same mail pieces 26% of the time. © 1996 John Wiley & Sons, Inc.     

Relevance of AIF/CypA Lethal Pathway in SH-SY5Y Cells Treated with Staurosporine

The AIF/CypA complex exerts a lethal activity in several rodent models of acute brain injury. Upon formation, it translocates into the nucleus of cells receiving apoptotic stimuli, inducing chromatin condensation, DNA fragmentation, and cell death by a caspase-independent mechanism. Inhibition of this complex in a model of glutamate-induced cell death in HT-22 neuronal cells by an AIF peptide (AIF(370-394)) mimicking the binding site on CypA, restores cell survival and prevents brain injury in neonatal mice undergoing hypoxia-ischemia without apparent toxicity. Here, we explore the effects of the peptide on SH-SY5Y neuroblastoma cells stimulated with staurosporine (STS), a cellular model widely used to study Parkinson’s disease (PD). This will pave the way to understanding the role of the complex and the potential therapeutic efficacy of inhibitors in PD. We find that AIF(370-394) confers resistance to STS-induced apoptosis in SH-SY5Y cells similar to that observed with CypA silencing and that the peptide works on the AIF/CypA translocation pathway and not on caspases activation. These findings suggest that the AIF/CypA complex is a promising target for developing novel therapeutic strategies against PD.     

Double and triple charge pumps with mos diodes: Dynamic models to an optimized design

In this paper the dynamic models of the double and triple charge pumps are extended to circuits in which the diodes are realized with an MOS transistor having a drain-gate contact. In this circuit realization we must take into account the influence of the source-substrate voltage on the threshold voltage V_t. The effects of the source-substrate voltage on the dynamic behaviour are analysed and discussed in detail. Moreover, simple equations allowing one to perform a pencil-and-paper area-efficient optimized design are developed from the two new models. The models obtained are also validated by SPICE simulation of the circuit assuming a typical CMOS 3 μm process.     

Synthesis,characterization, and degradation of block polyesteramides containing poly(L-lactide) segments

Random multiblock polyesteramides (PEAs) having polyester (PE) content of 20–50 wt % have been prepared by low-temperature polycondensation using sebacoyl chloride, 1,6-diaminohexane, and telechelic oligomers of L-lactide with M_n = 600–1500. The PEAs were characterized by IR and ¹H-NMR spectroscopy, wide-angle X-ray diffraction, and thermal analysis. Only the polyamide segments are able to crystallize, and the crystallinity depends on the composition and architecture of the PEAs. From viscosity and IR measurements it was established that the chain degradation of PEA powders or films suspended in buffer solutions occurs by hydrolysis of the ester linkages. The degradation rate is influenced by pH, PE content, and, to a lesser extent, by crystallinity. © 1992 John Wiley & Sons, Inc.     

Effects of Eltrombopag on In Vitro Macrophage Polarization in Pediatric Immune Thrombocytopenia

Immune Thrombocytopenia (ITP) is an autoimmune disease characterized by autoantibodies-mediated platelet destruction, a prevalence of M1 pro-inflammatory macrophage phenotype and an elevated T helper 1 and T helper 2 lymphocytes (Th1/Th2) ratio, resulting in impairment of inflammatory profile and immune response. Macrophages are immune cells, present as pro-inflammatory classically activated macrophages (M1) or as anti-inflammatory alternatively activated macrophages (M2). They have a key role in ITP, acting both as effector cells, phagocytizing platelets, and, as antigen presenting cells, stimulating auto-antibodies against platelets production. Eltrombopag (ELT) is a thrombopoietin receptor agonist licensed for chronic ITP to stimulate platelet production. Moreover, it improves T and B regulatory cells functions, suppresses T-cells activity, and inhibits monocytes activation. We analyzed the effect of ELT on macrophage phenotype polarization, proposing a new possible mechanism of action. We suggest it as a mediator of macrophage phenotype switch from the M1 pro-inflammatory type to the M2 anti-inflammatory one in paediatric patients with ITP, in order to reduce inflammatory state and restore the immune system function. Our results provide new insights into the therapy and the management of ITP, suggesting ELT also as immune-modulating drug.