Effect of Al2O3 Addition on Mineralogical Modification and Crystallization Kinetics of a High Basicity BOF Steel Slag

Metallurgical and Materials Transactions B - Basic oxygen furnace (BOF) steel slag is a main byproduct that is produced during the converter steelmaking process. The volume instability and fast...     

Polymers dynamics of the nonfluoro,nano-brush repelling agent with self-stratifying property in water-based coatings

While perfluoroalkyl acids (PFAAs), also known as C8s, are used extensively in textile repellent coatings, concerns have arisen for their carcinogenicity and hazardous effects on the environment. In this study, a novel water-based, nonfluoro, and nanobrush textile repelling agent was prepared by conventional sol–gel chemistry using amorphous fumed silica and n-octyltriethoxysilane as the starting materials. Minimal interaction between the designed repelling agent and marketed water-based resins was confirmed using linear viscosity region (LVR) analysis and asymmetric-flow field-flow fractionation (AF4), suggesting the self-stratification potential of the repelling agent. More specifically, the repelling agent exhibited excellent compatibility and self-stratifying ability with a force-emulsified acrylic-based resin, affording a water contact angle of 104.3° when incorporated at 7% solid content. Performance tests carried out on thermoplastic polyurethane (TPU) revealed excellent adhesion (100/100) of a final formulation, and a significant increase in water contact angle from 80.1° to 103.8° after treatment. In addition, the fouling area after the removal of a submerged sample from a mixture of slurry, polymer, and oil decreased from 48 to 1% when the repelling agent was added. Moreover, the sludge-fouling property remained unchanged after 1000 cycles of abrasion. These findings demonstrate the potential of the described nonfluoro, nanobrush repelling agent as an environmentally safe alternative for use with commercial resins, in turn realizing a fully water-based hydrophobic coating. © 2019 Wiley Periodicals, Inc. J. Appl. Polym. Sci. 2019 , 136, 48003.     

基于投影寻踪的径向基函数网络在参考腾发量预测中的应用

径向基函数网络(RBFN)已广泛应用于参考腾发量预测等领域，但常用的K均值聚类和自组织特征映射等方法在求取径向基函数网络隐层节点中心时存在较大不足。针对这一问题，本文引入投影寻踪方法，在投影降维的基础上实现对大量高维数据的聚类，建立了基于投影寻踪的径向基函数网络模型，并将该模型应用于山西潇河灌区参考腾发量的预测，研究了不同气象因子输入对参考腾发量预测精度的影响。结果表明，基于投影寻踪的径向基函数网络具有较强的适用性，只需使用最高温度、最低温度、日照时数和旬序数作为输入因子，就能以较高的精度预测参考腾发量。     

基于射频技术的无刷同步电机励磁电流的检测

无刷同步电机的励磁系统对励磁电流的测量是制约该励磁方式发展的一大障碍。设计了一个射频系统可以用来解决同步电机的励磁电流的测量问题。该系统可以方便地检测到同步电机励磁机的整流二极管的工作状态并且可以动态地显示励磁电流，极大地方便了运行人员做出判断，而且结构简单、方便实用。     

Growth Defects in Langasite Crystals Observed with White Beam Synchrotron Radiation Topography

Langasite single crystal was grown by the Czochralski method and its perfection was assessed by white beam synchrotron radiation topography. It is found that the growth core and the growth striations are the primary growth defects and they show strong X-ray kinematical contrast in the topographs. Another typical defect in LGS crystal is dislocation. The formation mechanisms of these growth defects in LGS crystals were discussed.     

变频器调速装置节能浅析

1概述 近十多年来,随着电力电子技术、微电子技术及现代控制理论的发展,变频调速技术已经广泛地用于交流电动机的速度控制,其最主要的特点是具有高效率的驱动性能及良好的控制特性.它是一种高新技术电力节能装置,它通过改变（降低）电源工作频率,来降低动力设备（电机）的转速,减少设备的输出功率,达到输出功率与工作负荷的最佳匹配,实现节能目的,有效地提高了经济效益和产品质量.几乎可以说,有电动机的地方就有变频器,在一切需要进行速度控制的场合,变频器以其操作方便、体积小、控制性能高而获得广泛应用.     

High-performance and power-efficient CMOS comparators

Several design techniques for high-performance and power-efficient CMOS comparators are proposed. First, the comparator is based on the priority-encoding (PE) algorithm, and the dynamic circuit technique developed specifically for the priority encoder can be applied. Second, the PE function and the subsequent logic functions are merged and efficiently realized in the multiple output domino logic (MODL) to result in a shortened logic depth. The circuit in MODL CMOS is also compact and power efficient because few transistors are needed. Third, the multilevel look-ahead technique is used to shorten the path of priority-token propagation. Finally, the circuit is realized with a latch-based two-stage pipelined structure, and the comparison function is partitioned into two parts, with each part executed in each half of the clock cycle in a delay-balanced manner. Post-layout simulation results show that a 64-b comparator designed with the proposed techniques in a 3-V 0.6-/spl mu/m CMOS technology is 16% faster, 50% smaller, and 79% more power efficient as compared with the all-n-transistor comparator, which is the fastest among the conventional comparators. Measurement results of the test chip conform with simulation results and prove the feasibility of the proposed techniques.