Salt Concentration Effects in Planar Light‐Emitting Electrochemical Cells

Incorporation of ions in the active layer of organic semiconductor devices may lead to attractive device properties like enhanced injection and improved carrier transport. In this paper, we investigate the effect of the salt concentration on the operation of light‐emitting electrochemical cells, using experiments and numerical calculations. The current density and light emission are shown to increase linearly with increasing ion concentration over a wide range of concentrations. The increasing current is accompanied by an ion redistribution, leading to a narrowing of the recombination zone. Hence, in absence of detrimental side reactions and doping‐related luminescence quenching, the ion concentration should be as high as possible.     

Steric Crowding Makes Challenging C(sp3)-F Reductive Eliminations Feasible

A high-yielding fluorination of (triphos)Pt-R(+) has been achieved using an array of F(+) sources, with XeF(2) yielding R-F in minutes. The C-F coupling proved to be a stereoretentive process that proceeds via a concerted reductive elimination from a putative dicationic Pt(IV) center. The larger the steric congestion of the (triphos)Pt-C(sp3) (+) complexes, the more efficient the fluorination, seemingly a result of sterically accelerated C-F reductive elimination along with simultaneous deceleration of its competing processes (β-H elimination).     

A residual-based a posteriori error estimator for a fully-mixed formulation of the Stokes–Darcy coupled problem

In this paper we develop an a posteriori error analysis of a new fully mixed finite element method for the coupling of fluid flow with porous media flow in 2D. Flows are governed by the Stokes and Darcy equations, respectively, and the corresponding transmission conditions are given by mass conservation, balance of normal forces, and the Beavers–Joseph–Saffman law. We consider dual-mixed formulations in both media, which yields the pseudostress and the velocity in the fluid, together with the velocity and the pressure in the porous medium, and the traces of the porous media pressure and the fluid velocity on the interface, as the resulting unknowns. The set of feasible finite element subspaces includes Raviart–Thomas elements of lowest order and piecewise constants for the velocities and pressures, respectively, in both domains, together with continuous piecewise linear elements for the traces. We derive a reliable and efficient residual-based a posteriori error estimator for the coupled problem. The proof of reliability makes use of the global inf–sup condition, Helmholtz decompositions in both media, and local approximation properties of the Clément interpolant and Raviart–Thomas operator. On the other hand, inverse inequalities, the localization technique based on element-bubble and edge-bubble functions, and known results from previous works, are the main tools for proving the efficiency of the estimator. Finally, some numerical results confirming the theoretical properties of this estimator, and illustrating the capability of the corresponding adaptive algorithm to localize the singularities of the solution, are reported.     

AES for multiscale localization modeling in granular media

This work presents a multiscale strong discontinuity approach to tackle key challenges in modeling localization behavior in granular media: accommodation of discontinuities in the kinematic fields, and direct linkage to the underlying grain-scale information. Assumed enhanced strain (AES) concepts are borrowed to enhance elements for post-localization analysis, but are reformulated within a recently-proposed hierarchical multiscale computational framework. Unlike classical AES methods, where material properties are usually constants or assumed to evolve with some arbitrary phenomenological laws, this framework provides a bridge to extract evolutions of key material parameters, such as friction and dilatancy, based on grain scale computational or experimental data. More importantly, the phenomenological softening modulus typically used in AES methods is no longer required. Numerical examples of plane strain compression tests are presented to illustrate the applicability of this method and to analyze its numerical performance.     

Modeling microwave power structures based on k-furcated waveguides arbitrarily filled with materials by modal techniques.

Waveguide structures are very popular in the microwave power industry due to their power handling capabilities. Modal expansion of the waveguide fields and application of the circuit theory allow for the division of a complex device into several simpler sections which can be analyzed separately with the best suited method. The modal techniques can be divided into two groups--those which analyze junctions or discontinuities and those which examine propagation characteristics. In this paper, a review of modal techniques for high power applications is given. Modal expansion of the fields in the waveguides is then performed and applied to modeling of k-furcated waveguides. The modal analysis based on the Coupled Mode Method is described for the waveguides partially filled with isotropic materials. A hybrid modal analysis coupled with Finite Element Method suitable for more complex waveguide structures is also described. Computational results obtained for some real-life microwave devices are presented. Excellent agreement was found when comparing the results with those generated with a commercial FDTD simulator demonstrates the validity and reliability of the proposed method.     

IEEE-Compliant IDCT on FPGA-Augmented TriMedia

This paper presents a TriMedia processor extended with an IDCT reconfigurable design, and assesses the performance gain such an extension has when performing MPEG-2 decoding. We first propose the skeleton of an extension of the TriMedia architecture, which consists of a Field-Programmable Gate Array (FPGA)-based Reconfigurable Functional Unit (RFU), a Configuration Unit managing the reconfiguration of the RFU, and their associated instructions. Then, we address the computation of the 8 × 8 (2-D) IDCT on such extended TriMedia and propose a scheme to implement the 1-D IDCT operation on the RFU. When mapped on an ACEX EP1K100 FPGA from Altera, the proposed 1-D IDCT exhibits a latency of 16 and a recovery of 2 TriMedia@200 MHz cycles, and occupies 45% of the logic cells of the device. By configuring the 1-D IDCT on the RFU at application launch-time, the IEEE-compliant 2-D IDCT can be computed with the throughput of 1/32 IDCT/cycle. This figure translates to an improvement over the standard TriMedia of more than 40% in terms of computing time when 2-D IDCT is carried out in the framework of MPEG-2 decoding. Finally, the proposed reconfigurable IDCT is compared to a number of existing designs.Mihai Sima was born in Bucharest, Romania. He received the MS degree in Electrical Engineering from Politehnica University of Bucharest, and the Ph.D. degree in Electrical Engineering from Delft University of Technology, The Netherlands. He had been with the Microelectronics Company in Bucharest for 3 years, where he was involved in instrumentation electronics for integrated circuit testing. Subsequently, he joined the Telecommunications Department of Politehnica University of Bucharest, where he had been involved in digital signal processing and speech recognition for 6 years. More recently, he had been with the Faculty of Electrical Engineering, Mathematics, and Computer Science, Delft University of Technology, where he worked on reconfigurable architectures for mediaprocessing domain. He is currently an assistant professor with the Department of Electrical and Computer Engineering, University of Victoria, B.C., Canada. His research interests include computer architecture, reconfigurable computing, embedded systems, digital signal processing, and speech recognition.Sorin D. Coofan was born in Mizil, Romania. He received the MS degree in Computer Science from the Politehnica University of Bucharest, Romania, and the Ph.D. degree in Electrical Engineering from Delft University of Technology, The Netherlands. He had worked with the Research & Development Institute for Electronic Components (ICCE) in Bucharest for a decade, being involved in structured design of digital systems, design rule checking of ICs layout, logic and mixed-mode simulation of electronic circuits, testability analysis, and image processing. He is currently an associate professor with the Faculty of Electrical Engineering, Mathematics, and Computer Science, Delft University of Technology, The Netherlands. His research interests include computer arithmetic, parallel architectures, embedded systems, reconfigurable computing, nano-electronics, neural networks, computational geometry, and computer aided design.Jos T.J. van Eijndhoven was born in Roosendaal, The Netherlands. He studied Electrical Engineering at the Eindhoven University of Technology, The Netherlands, obtaining the M.Sc. and Ph.D. degrees in 1981 and 1984, respectively, for a work on piecewise linear circuit simulation. Then, he became a senior research member in the design automation group of the Eindhoven University of Technology. In 1986 he spent a sabbatical period at the IBM Thomas J. Watson Research Laboratory, Yorktown Heights, New York, for research on high level synthesis. In 1998 he joined Philips Research Laboratories in Eindhoven, The Netherlands, to work on the architectural design of programmable multimedia hardware and the associated mapping of media processing applications.Stamatis Vassiliadis was born in Manolates, Samos, Greece. He is a professor with the Faculty of Electrical Engineering, Mathematics, and Computer Science, Delft University of Technology, The Netherlands. He has also served in the faculties of Cornell University, Ithaca, NY, and the State University of New York (S.U.N.Y.), Binghamton, NY.He hadworked for a decade with IBM in the AdvancedWorkstations and Systems laboratory in Austin TX, the Mid-Hudson Valley Laboratory in Poughkeepsie, NY, and the Glendale Laboratory in Endicott, NY. In IBM he was involved in a number of projects regarding computer design, organizations, and architectures and the leadership to advanced research projects. A number of his design and implementation proposals have been implemented in commerciallyavailable systems and processors including the IBM 9370 model 60 computer system, the IBM POWER II, the IBM AS/400 Models 400, 500, and 510, Server Models 40S and 50S, the IBM AS/400 Advanced 36, and the IBM S/390 G4 and G5 computer systems. For his work, he received numerous awards including 23 levels of Publication Achievement Awards, 15 levels of Invention Achievement Awards and an Outstanding Innovation Award for Engineering/Scientific Hardware Design in 1989. In 1990 he has been awarded the highest number of USA patents in IBM, six of his 70 USA patents being rated with the highest patent ranking in IBM.Kees A. Vissers graduated the Delft University of Technology, receiving his M.Sc. in 1980. He started directly with Philips Research Laboratories in Eindhoven where he was involved in highlevel simulation and high-level synthesis. He had been heading the research on hardware/software co-design and system level design for many years, and had a significant contribution to the TriMedia VLIW processor. From 1987 till 1988 he was a visiting researcher at Carnegie Mellon University, Pittsburgh, Pennsylvania, with the group of Don Thomas. He is currently a Research Fellow with University of California at Berkeley, Department of Electrical Engineering and Computer Sciences. His research interests include video processing, embedded media processing systems, and reconfigurable computing.