BiCMOS logic circuit for single-battery operation

A novel BiCMOS logic circuit is described that provides highspeed rail-to-rail operation with only one battery cell (1-1.5 V). The proposed circuit utilises a novel pull-down scheme that involves bootstrapping the base of the pull-down p-n-p bipolar junction transistor to a negative potential during the pull-down transient period. Circuit simulations have shown that the proposed circuit outperforms the transient-saturation full-swing BiCMOS and the bootstrapped bipolar circuits in terms of delay, power and cross-over capacitance for all simulated supply voltages     

BiCMOS circuit optimisation technique linking channel width of MOSdevice to collector design of BJT

A methodology to optimise the propagation delay of BICMOS/BiNMOS circuits for high level injection is proposed. It is based on modifying the collector design of the BJT in association with an increase in the channel width of the MOS device to account for the speed degradation caused by the onset of high level injection. A sensitivity-type approach has been adopted to link the value of the channel width of the MOS device to the collector profile of the BJT