Throughput performance of an FHMA system with variable rate coding

We compare throughput bounds for a frequency-hopped multiple-access (FHMA) system employing variable rate as well as fixed rate coding (FRC). Nonfading as well as Rayleigh-fading channels are explored. The throughput bounds for the variable rate coding (VRC) schemes are based on the assumption that the number of active users in the system, m, is known at any time while the bounds for the FRC scheme assumes that the fixed code rate is optimized for the user population mean, λ, where the population is assumed to be Poisson distributed. We present bounds for theoretical “perfect” codes which achieve the capacity as well as bounds for Reed-Solomon (RS) codes of practical block lengths. Finally, we show the dependence of a VRC scheme upon the accuracy of the estimates of m and present a general comparison of the gains of using VRC versus a realistic FRC scheme     

Performance Analysis of the UPC/NPC Algorithm for Guaranteed QoS in ATM Networks

It is well known that if usage parameter control/network parameter control (UPC/NPC) functions are used together with a cell loss priority control scheme in ATM networks, the measurement phasing problem can occur. This makes it difficult for a network provider to define and commit the cell loss ratio as a QoS parameter. To solve the problem, we propose a new UPC/NPC algorithm. By using the proposed UPC/NPC algorithm, we can define the cell loss ratios for CLP = 0 and CLP = 0+1 cell streams without the measurement phasing problem under any conditions. We analyzed the performance of the proposed UPC/NPC algorithm. Using a discrete time model for the UPC/NPC architecture with a discrete-time semi-Markov process (DSMP) input model, we obtained the cell discarding probabilities of CLP = 0 and CLP = 0+1 cell streams and showed that more CLP = 0 cells are accepted compared to what was proposed in ITU-T.     

An efficient synthesis technique of tapered transmission line withloss and dispersion

A synthesis technique of lossy and dispersive tapered transmission line is presented that extends lossless cases suggested by Klopfenstein and others. A special optimization process based on the Fourier transform pair and generalized Taylor's procedure is performed to extract the exact null points of lobe-like frequency response in terms of the input reflection coefficient of lossy-tapered line in which the loss may be frequency dependent and distance dependent. The theory is verified by evaluation of a synthesized microstrip taper profile in the lossy case and is expected to be helpful for design of tapered line in the high-frequency microwave integrated circuits (MICs) with loss     

Modeling and simulation of 2D lithium‐ion solid state battery

The goal of the work presented here was to develop a simulation approach for studying the effects of materials and geometry on the performance of Li‐ion Solid State Batteries (SSB). Simulation provides the opportunity to explore, with ease, different material properties and cell geometries to optimize a Li‐ion SSB's performance. Simulations shown in this paper are time‐dependent and consider electrochemical reaction, heat transfer, the diffusion of Li‐ions and electrons in the electrolyte, and solid Li diffusion in the positive electrode. A 2D model was simulated and the results shown. The simulations were able to show discharge curves, heat flux, the concentration of Li‐ions, electrons, and solid Li at any time in the discharge cycle. Copyright © 2015 John Wiley & Sons, Ltd.     

CuPc/PbZr0.2Ti0.8O3/(La,Ba)MnO3 field effect transistor heterojunction photomemory

We investigated a photoconductor(PC)/ferroelectric oxide(OF)/semiconductor oxide(SO) POS-FET structure photomemory consisting of organic photoconductor CuPc/inorganic ferroelectric PbZr_0.2Ti_0.8O₃ heterojunction gate and a ferromagnetic oxide semiconductor La_0.87Ba_0.13MnO₃ channel. Visible light information detected by photoconductor CuPc can be memorized in ferroelectric PbZr_0.2Ti_0.8O₃, and non-volatile and non-destructive reading out process of light information memorized in this ferroelectric layer were achieved by reading out the resistance modulation of ferromagnetic semiconductor oxide La_0.87Ba_0.13MnO₃ channel under the photoconductor/ferroelectric gate.     

The leakage current improvement in an ultrashallow junction NMOSwith Co silicided source and drain

The leakage current characteristics of the cobalt silicided NMOS transistors with a junction depth of 800 Å have been studied. In order to minimize the junction leakage current, the thickness of the CoSi₂ layer should he controlled under 300 Å and the Si surface damage induced by the gate spacer etch should be minimized. The post furnace annealing after the second silicidation by the rapid thermal annealing (RTA) process also affected the leakage current characteristics. The gate induced drain leakage (GIDL) current was not affected by the lateral encroachment of CoSi₂ layer into the channel direction when the gate spacer length was larger than 400 Å     

Optimal shape design of microwave device using FDTD and designsensitivity analysis

In this paper, a novel optimal shape design method is proposed using the finite-difference time-domain (FDTD) method and the design sensitivity analysis to obtain broad-band characteristics of microwave devices. In shape design problem, the nodes that describe the shape of geometry to be optimized are taken as design variables. The design sensitivity is evaluated using the adjoint variable equation that is obtained from a terminal-value problem. The adjoint equation can be solved by the FDTD technique with the backward time scheme. With this method, a Ka-band unilateral fin line is tested to show validity     

A single-chip storage LSI for home networks

Network direct attached storage (NDAS) is a network storage architecture that allows direct attachment of existing ATA/ATAPI devices to Ethernet without a separate server. Unlike other architectures such as NAS, SAN, and USB mass storage, no server computer intervenes between the storage and the client hosts. We describe an NDAS disk controller (NDC) amenable to low-cost single-chip implementation that processes a simplified L3/L4 protocol and converts commands between ATA/ATAPI and Ethernet, while the remaining complex tasks are performed by remote hosts. Unlike NAS architectures that use TCP/IP, NDAS uses a TCP-like lean protocol that lends itself well to high-performance hardware realization. Thanks to the simple NDAS architecture and protocol, an NDC implemented on a single 4 mm /spl times/ 4 mm chip in 0.18 /spl mu/m CMOS technology achieves a maximum throughput of 55 Mbytes/s on gigabit Ethernet, which is comparable to that of a high-performance disk locally attached to a host computer.     

Research activities on next-generation mobile communications and services in Korea

In this article we present a perspective on next-generation mobile communications and services. As a preliminary research work on next-generation mobile communications, we exploit what next-generation mobile services will be (S. Ryu et al., May 2003). We define next-generation mobile services as a hierarchy of services consisting of three different service levels: the service areas, the service functionalities, and the service technologies. We derive these service levels by means of scenario-based analysis. Next we propose conceptual reference network architecture, focusing on the realization of the service technologies. We divide the network into four different parts: a user equipments and access part, a network service provisioning layer part, a network control layer part, and non-mobile network operator service pan, according to characteristics of information and service flows within a network. In this reference network architecture, service elements such as servers, processors, and gateways are placed in each network part to support the derived next-generation mobile services. Finally, we give a brief introduction of research and development activities for next-generation mobile communication systems and services in Korea.     

A 4-MB on-chip L2 cache for a 90-nm 1.6-GHz 64-bit microprocessor

A 4-MB L2 data cache was implemented for a 64-bit 1.6-GHz SPARC(r) RISC microprocessor. Static sense amplifiers were used in the SRAM arrays and for global data repeaters, resulting in robust and flexible timing operation. Elimination of the global clock grid over the SRAM array saves power, enabled by combining the clock information with array select signals. Redundancy was implemented flexibly, with shift circuits outside the main data array for area efficiency. The chip integrates 315 million transistors and uses an 8-metal-layer 90-nm CMOS process.