The leakage current improvement in an ultrashallow junction NMOSwith Co silicided source and drain

The leakage current characteristics of the cobalt silicided NMOS transistors with a junction depth of 800 Å have been studied. In order to minimize the junction leakage current, the thickness of the CoSi₂ layer should he controlled under 300 Å and the Si surface damage induced by the gate spacer etch should be minimized. The post furnace annealing after the second silicidation by the rapid thermal annealing (RTA) process also affected the leakage current characteristics. The gate induced drain leakage (GIDL) current was not affected by the lateral encroachment of CoSi₂ layer into the channel direction when the gate spacer length was larger than 400 Å     

Optimal shape design of microwave device using FDTD and designsensitivity analysis

In this paper, a novel optimal shape design method is proposed using the finite-difference time-domain (FDTD) method and the design sensitivity analysis to obtain broad-band characteristics of microwave devices. In shape design problem, the nodes that describe the shape of geometry to be optimized are taken as design variables. The design sensitivity is evaluated using the adjoint variable equation that is obtained from a terminal-value problem. The adjoint equation can be solved by the FDTD technique with the backward time scheme. With this method, a Ka-band unilateral fin line is tested to show validity     

A single-chip storage LSI for home networks

Network direct attached storage (NDAS) is a network storage architecture that allows direct attachment of existing ATA/ATAPI devices to Ethernet without a separate server. Unlike other architectures such as NAS, SAN, and USB mass storage, no server computer intervenes between the storage and the client hosts. We describe an NDAS disk controller (NDC) amenable to low-cost single-chip implementation that processes a simplified L3/L4 protocol and converts commands between ATA/ATAPI and Ethernet, while the remaining complex tasks are performed by remote hosts. Unlike NAS architectures that use TCP/IP, NDAS uses a TCP-like lean protocol that lends itself well to high-performance hardware realization. Thanks to the simple NDAS architecture and protocol, an NDC implemented on a single 4 mm /spl times/ 4 mm chip in 0.18 /spl mu/m CMOS technology achieves a maximum throughput of 55 Mbytes/s on gigabit Ethernet, which is comparable to that of a high-performance disk locally attached to a host computer.     

Research activities on next-generation mobile communications and services in Korea

In this article we present a perspective on next-generation mobile communications and services. As a preliminary research work on next-generation mobile communications, we exploit what next-generation mobile services will be (S. Ryu et al., May 2003). We define next-generation mobile services as a hierarchy of services consisting of three different service levels: the service areas, the service functionalities, and the service technologies. We derive these service levels by means of scenario-based analysis. Next we propose conceptual reference network architecture, focusing on the realization of the service technologies. We divide the network into four different parts: a user equipments and access part, a network service provisioning layer part, a network control layer part, and non-mobile network operator service pan, according to characteristics of information and service flows within a network. In this reference network architecture, service elements such as servers, processors, and gateways are placed in each network part to support the derived next-generation mobile services. Finally, we give a brief introduction of research and development activities for next-generation mobile communication systems and services in Korea.     

A 4-MB on-chip L2 cache for a 90-nm 1.6-GHz 64-bit microprocessor

A 4-MB L2 data cache was implemented for a 64-bit 1.6-GHz SPARC(r) RISC microprocessor. Static sense amplifiers were used in the SRAM arrays and for global data repeaters, resulting in robust and flexible timing operation. Elimination of the global clock grid over the SRAM array saves power, enabled by combining the clock information with array select signals. Redundancy was implemented flexibly, with shift circuits outside the main data array for area efficiency. The chip integrates 315 million transistors and uses an 8-metal-layer 90-nm CMOS process.     

Comments on "optimal approximation of uniformly rotated images:relationship between Karhumen-Loeve expansion and discrete cosinetransform"

This paper points out the incorrect expressions of Uenohara and Kanade (see ibid., vol.7, p.116-19, 1998), in the context of the representation of the eigenvectors based on the discrete cosine transform (DCT). With the repeated eigenvalues, the eigenvector matrix of the PxP real symmetric circulant matrix can be constructed using the singular value decomposition (SVD), where P denotes the number of uniformly rotated images. Or equivalently it can be formulated in terms of the discrete Hartley transform (DHT). An example with P=4 is presented to show the correctness of our analysis.     

Controller for digital audio power amplifier with bit stream input

A new controller for a digital audio amplifier with bit stream input is proposed. The proposed controller has excellent features such as wide error correction range and no limitation on the modulation index. The controller is implemented in the half-bridge class-D amplifier and performance is verified through experiments.     

Visual Cryptography Based on an Interferometric Encryption Technique

This paper presents a new method for a visual cryptography scheme that uses phase masks and an interferometer. To encrypt a binary image, we divided it into an arbitrary number of slides and encrypted them using an XOR process with a random key or keys. The phase mask for each encrypted image was fabricated under the proposed phase‐assignment rule. For decryption, phase masks were placed on any path of the Mach‐Zehnder interferometer. Through optical experiments, we confirmed that a secret binary image that was sliced could be recovered by the proposed method.     

An efficient frequency offset estimator for OFDM systems and itsperformance characteristics

In this paper, we propose a new frequency synchronization algorithm for orthogonal frequency division multiplexing (OFDM) systems requiring only one training symbol, based on a conventional method which requires two training symbols. While the timing synchronization is obtained by using the conventional method, the carrier frequency offset is efficiently estimated by the proposed method. It is shown that the proposed method not only reduces the number of the training symbols but also possesses better performance than the conventional method without increase in complexity     

Effects of Nd2O3 and TiO2 Addition on the Microstructures and Microwave Dielectric Properties of BaO-Nd2O3-TiO2 System

The effects of Nd₂O₃ and TiO₂ addition on the microstructures and microwave dielectic properties of BaO-Nd₂O₃-TiO₂ system were investigated. BaNd₂Ti₄O₁₂ or BaNd₂Ti₅O₁₄ phases were observed for compositions based on BaO/Nd₂O₃ = 1 ratio. The compositions deviated from BaO/Nd₂O₃ = 1 ratio were composed of major phases of BaNd₂Ti₄O₁₂ or BaNd₂Ti₅O₁₄, and the compound of Nd₂O₃ and TiO₂ (Nd₂Ti₂O₇) or that of BaO and TiO₂ (BaTi₄O₉). The microstructure of ceramic with BaO·Nd₂O₃ ·4TiO₂ composition varied from spherical grains to needlelike grains with increasing sintering temperature. With increasing Nd₂O₃, the optimum sintering temperature with maximum density increased, and the dielectric constant( · _r) and quality factor(Q) decreased due to the formation of secondary phases. With increasing TiO_2/ the optimum sintering temperature and the dielectric constant decreased with increased Q value. And the temperature coefficient of resonant frequency, ·_f shifted toward positive direction. The dielectric ceramics with BaO/Nd₂O₃ = 1 showed Q values of above 2000 and dielectric constants of above 80 at 3GHz.