排序方式: 共有52条查询结果,搜索用时 781 毫秒
41.
Prakasam P.K. Kulkarni M. Xi Chen Zhuizhuan Yu Hoyos S. Silva-Martinez J. Sanchez-Sinencio E. 《Circuits and Systems II: Express Briefs, IEEE Transactions on》2008,55(4):309-313
Transform-domain (TD) receivers expand the received signal over a basis set, and then operate on the basis coefficients. An analog computation of the basis coefficients efficiently parallelizes the signal for digital processing, relaxing the sampling requirements and enabling parallel digital processing at a much lower rate. Frequency-domain (FD) sampling, as a special case of TD sampling, has been proposed to parallelize the sampling process in broad-band communication receivers. The flexibility and scalability of TD receivers allow for the design of receivers that can cope with a large range of narrow-band and broad-band communications standards. A theoretical TD receiver design example is provided which is capable of processing GSM, Bluetooth, IEEE802.11g, Wimax, and UWB in just one configurable front-end. An example of spectrum sensing in cognitive radio is also provided. 相似文献
42.
An On-Chip Loopback Block for RF Transceiver Built-In Test 总被引:1,自引:0,他引:1
Onabajo M. Silva-Martinez J. Fernandez F. Sanchez-Sinencio E. 《Circuits and Systems II: Express Briefs, IEEE Transactions on》2009,56(6):444-448
This brief addresses the realization of an on-chip block for built-in testing of RF transceivers with the loopback method. Design issues and measurement results are discussed, giving practical insights into closing the signal path between transmitter (Tx) and receiver (Rx) sections. The circuit is intended for cost-efficient production testing of RF front-end blocks with on-chip power detectors and bit-error-rate analysis at baseband frequencies for integrated transceivers operating in the 1.9- to 2.4-GHz range. It can provide 40-200 MHz Tx-Rx frequency shifting and 26-42 dB continuous attenuation while consuming a 0.052-mm2 die area in 0.13-mum CMOS technology and ~ 12 mW of power when activated in test mode. 相似文献
43.
Silva-Martinez J. Adut J. Rocha-Perez J.M. Robinson M. Rokhsaz S. 《Solid-State Circuits, IEEE Journal of》2003,38(2):216-225
A full CMOS seventh-order linear phase filter based on g/sub m/-C biquads with a -3-dB frequency of 200 MHz is realized in 0.35-/spl mu/m CMOS process. The linear operational transconductance amplifier is based on complementary differential pairs in order to achieve both low-distortion figures and high-frequency operation. The common-mode feedback (CMFB) employed takes advantage of the filter architecture; incorporating the load capacitors into the CMFB loop improves further its phase margin. A very simple automatic tuning system corrects the filter deviations due to process parameter tolerances and temperature variations. The group delay ripple is less than 5% for frequencies up to 300 MHz, while the power consumption is 60 mW. The third-harmonic distortion is less than -44 dB for input signals up to 500 mV/sub pp/. The filter active area is only 900 /spl times/ 200 /spl mu/m/sup 2/. The supply voltages used are /spl plusmn/1.5 V. 相似文献
44.
A multistage operational transconductance amplifier with a feedforward compensation scheme which does not use Miller capacitors is introduced. The compensation scheme uses the positive phase shift of left-half-plane (LHP) zeroes caused by the feedforward path to cancel the negative phase shift of poles to achieve a good phase margin. A two-stage path increases further the low frequency gain while a feedforward single-stage amplifier makes the circuit faster. The amplifier bandwidth is not compromised by the absence of the traditional pole-splitting effect of Miller compensation, resulting in a high-gain wideband amplifier. The capacitors of a capacitive amplifier using the proposed techniques can be varied more than a decade without significant settling time degradation. Experimental results for a prototype fabricated in an AMI 0.5-/spl mu/m CMOS process show DC gain of around 90 dB and a 1% settling time of 15 ns for a load capacitor of 12 pF. The power supply used is /spl plusmn/1.25 V. 相似文献
45.
Veeravalli A. Sanchez-Sinencio E. Silva-Martinez J. 《Solid-State Circuits, IEEE Journal of》2002,37(6):770-775
A family of CMOS operational transconductance amplifiers (OTAs) has been designed for very small Gm's (of the order of nanoamperes per volt) with transistors operating in moderate inversion. Several OTA design schemes such as conventional, using current division, floating-gate, and bulk-driven techniques are discussed. A detailed comparison has also been made among these schemes in terms of performance characteristics such as power consumption, active silicon area, and signal-to-noise ratio. The transconductance amplifiers have been fabricated in a 1.2-μm n-well CMOS process and operate at a power supply of 2.7 V. Chip test results are in good agreement with theoretical results 相似文献
46.
Attenuation-Predistortion Linearization of CMOS OTAs With Digital Correction of Process Variations in OTA-C Filter Applications 总被引:2,自引:0,他引:2
Mobarak M. Onabajo M. Silva-Martinez J. Sanchez-Sinencio E. 《Solid-State Circuits, IEEE Journal of》2010,45(2):351-367
47.
Marvin Onabajo Jose Silva-Martinez 《Analog Integrated Circuits and Signal Processing》2012,70(3):429-435
An analog calibration technique is presented to improve the parameter matching between transistors in the differential high-frequency
signal path of analog CMOS circuits. It can be applied for mismatch reduction in differential broadband amplifiers and direct
down-conversion mixers in which short-channel devices are utilized to minimize bandwidth reduction from parasitic capacitances.
In general, the proposed methodology is suitable for radio frequency (RF) applications in which direct matching of the transistors
is undesired because sophisticated layout practices would increase the coupling between the high-frequency paths. The approach
involves auxiliary devices which sense the existing mismatch as part of a feedback loop for error minimization. This technique
is demonstrated with a differential amplifier that has a loaded gain and −3 dB frequency of 12.9 dB and 2.14 GHz, respectively.
It was designed in 90 nm CMOS technology with a 1.2 V supply. Monte Carlo simulations indicate that the 4.06 mV standard deviation
of the amplifier’s anticipated input-referred offset voltage improves to 0.76–1.28 mV with the mismatch reduction loop, which
is contingent on the layout configuration of the calibration circuitry. The associated drain current mismatch reduction for
the transistor pair under calibration in the amplifier core is from 3.1% to 0.6–1.0%. 相似文献
48.
F. Silva-Rivas C.-Y. Lu P. Kode B. K. Thandri J. Silva-Martinez 《Analog Integrated Circuits and Signal Processing》2009,59(1):91-95
In this paper, a calibration technique for Noise Transfer Function (NTF) optimization of Continuous-Time Bandpass Sigma Delta
(CT BP ΣΔ) modulators is presented. The proposed technique employs a test tone applied at the input of the quantizer to evaluate
the noise transfer function of the Analog-to-Digital Converter (ADC) using the capabilities of the Digital Signal Processing
(DSP) platform usually available in mixed-mode systems. Once the ADC output bit stream is captured, necessary information
to generate the control signals to tune the ADC parameters for best Signal-to-Quantization Noise Ratio (SQNR) performance
is extracted via an LMS software-based algorithm. Simulation results show that notch frequency of the NTF due to process variations
and temperature tolerances can be tuned using the proposed methodology. The proposed global calibration approach can be used
during the system start-up and the idle system time. The proposed approach uses a single in-band calibration tone, but it
can be expanded using out-of band test tones for background calibration schemes. 相似文献
49.
Hernandez-Garduno D. Silva-Martinez J. Ausin J. L. 《Circuits and Systems II: Express Briefs, IEEE Transactions on》2007,54(5):387-391
The periodical nonuniform individual sampling scheme has been shown suitable for capacitance spread and total capacitor area reduction in high quality (Q) factor switched-capacitor (SC) filters. However, the use of periodical nonuniform clock signals results in additional aliasing components in the output spectrum. This paper presents a simple model to analyze the generation of such alias components and gives practical expressions to estimate their power. The results are verified through circuit simulation of a 10.7-MHz second-order SC bandpass filter in a 0.35-mum CMOS technology. Implications on the use of this technique in the design of intermediate-frequency filters are discussed 相似文献
50.
A modified CMFB circuit is presented that reinstates the use of direct opamp auto-zeroing offset cancellation techniques in low voltage applications. This approach is particularly useful for high precision sample and hold amplifiers and Nyquist rate ADCs, where the opamp is reset during one of the clock phases. Differential offsets up to 50 mV are effectively reduced as demonstrated by a sample and hold example. 相似文献