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41.
Moshovos A. Sohi G.S. 《Proceedings of the IEEE. Institute of Electrical and Electronics Engineers》2001,89(11):1560-1575
Semiconductor technology scaling provides faster and more plentiful transistors to build microprocessors, and applications continue to drive the demand for more powerful microprocessors. Weaving the raw semiconductor material into a microprocessor that offers the performance needed by modern and future applications is the role of computer architecture. This paper overviews some of the microarchitectural techniques that empower modem high-performance microprocessors. The techniques are classified into: 1) techniques meant to increase the concurrency in instruction processing, while maintaining the appearance of sequential processing and 2) techniques that exploit program behavior. The first category includes pipelining, superscalar execution, out-of-order execution, register renaming, and techniques to overlap memory-accessing instructions. The second category includes memory hierarchies, branch predictors, trace caches, and memory-dependence predictors. The paper also discusses microarchitectural techniques likely to be used in future microprocessors, including data value speculation and instruction reuse, microarchitectures with multiple sequencers and thread-level speculation, and microarchitectural techniques for tackling the problems of power consumption and reliability 相似文献
42.
Nitin Mittal Urvinder Singh Rohit Salgotra Balwinder Singh Sohi 《Wireless Networks》2018,24(6):2093-2109
Wireless sensor network (WSN) consists of densely distributed nodes that are deployed to observe and react to events within the sensor field. In WSNs, energy management and network lifetime optimization are major issues in the designing of cluster-based routing protocols. Clustering is an efficient data gathering technique that effectively reduces the energy consumption by organizing nodes into groups. However, in clustering protocols, cluster heads (CHs) bear additional load for coordinating various activities within the cluster. Improper selection of CHs causes increased energy consumption and also degrades the performance of WSN. Therefore, proper CH selection and their load balancing using efficient routing protocol is a critical aspect for long run operation of WSN. Clustering a network with proper load balancing is an NP-hard problem. To solve such problems having vast search area, optimization algorithm is the preeminent possible solution. Spider monkey optimization (SMO) is a relatively new nature inspired evolutionary algorithm based on the foraging behaviour of spider monkeys. It has proved its worth for benchmark functions optimization and antenna design problems. In this paper, SMO based threshold-sensitive energy-efficient clustering protocol is proposed to prolong network lifetime with an intend to extend the stability period of the network. Dual-hop communication between CHs and BS is utilized to achieve load balancing of distant CHs and energy minimization. The results demonstrate that the proposed protocol significantly outperforms existing protocols in terms of energy consumption, system lifetime and stability period. 相似文献
43.
Cells from three insect cell lines responded to the enzyme-digested delta endotoxin of Bacillus thuringiensis with swelling, lysis, and vesicle formation. Sufficient toxin was taken up in 1 minute to cause half-maximal cell damage. Cytoxic activity was neutralized by specific antiserum to the endotoxin. 相似文献
44.
Rajan Sharma Nitin Mittal Balwinder Singh Sohi 《International Journal of Communication Systems》2020,33(7)
The advances in the size, cost of deployment, and user‐friendly interface of wireless sensor devices have given rise to many wireless sensor network (WSN) applications. WSNs need to use protocols for transmitting data samples from event regions to sink through minimum cost links. Clustering is a commonly used method of data aggregation in which nodes are organized into groups to reduce energy consumption. Nonetheless, cluster head (CH) has to bear an additional load in clustering protocols to organize different activities within the cluster. Proper CH selection and load balancing using efficient routing protocol is therefore a critical aspect for WSN's long‐term operation. In this paper, a threshold‐sensitive energy‐efficient cluster‐based routing protocol based on flower pollination algorithm (FPA) is proposed to extend the network's stability period. Using FPA, multihop communication between CHs and base station is used to achieve optimal link costs for load balancing distant CHs and energy minimization. Analysis and simulation results show that the proposed algorithm significantly outperforms competitive clustering algorithms in terms of energy consumption, stability period, and system lifetime. 相似文献
45.
Effects of TIG Surface Melting and Chromium Surface Alloying on Microstructure, Hardness and Wear Resistance of ADI 总被引:1,自引:0,他引:1
Microhardness and wear resistance of different rnicrostructures formed by TIG (tungsten inert gas) surface melting and chromium surface alloying (using ferrochromium) of ADI (austempered ductile iron) were studied. Surface melting resulted in the formation of a ledeburitic structure in the melted zone, and this structure has a hardness up to 896 HV as compared to 360 HV in that of ADI. Moreover, chromium surface alloying resulted in the formation of different structures including: (1) a hypereutectic structure consisting of primary (Fe,Cr)7C3 carbides and a eutectic matrix of transformed austenite (into martensite and retained austenite), as also (Fe,Cr)7C3 carbides, with a hardness of 1078 HV; (2) a hypoeutectic structure consisting of the same eutectic along with transformed primary austenite, with a hardness of 755 HV; and (3) a ledeburitic structure with an acicular morphology and a hardness of 896 HV. The results also indicated that surface melting reduced the wear rate of the ADI by approximately 37%. Also, chromium surface alloying yielded a superior wear behavior and reduced the wear rate of the treated specimens by about 38% and 70%, depending on the structures formed. 相似文献
46.
Carbon black, short carbon fiber (SCF), and multiwall carbon nano‐tube (MWNT)‐filled conductive composites were prepared from ethylene vinyl acetate copolymer. The dielectric property and electromagnetic interference (EMI) shielding of carbon black, MWNT, and SCF‐filled composites were studied with different filler loadings. The dielectric constant and loss of filled polymer composites is due to the formation of interfacial polarization in the polymer matrix. It was found that the dielectric constant, dielectric loss, and EMI shielding of filled composites depends on amount and type of filler loading. The results of different experiments have been discussed in the light of break down and formation of continuous conductive network in polymer matrix. The results indicate that these composites can be used as effective EMI shielding materials. POLYM. COMPOS., 2011. © 2011 Society of Plastics Engineers. 相似文献
47.
In this study the corrosion resistance of chromium and nickel single layers and multilayer coatings of nanolayered Cr/Ni, electrodeposited from Cr(III)-Ni(II) baths on low carbon steel substrates, has been studied. The coatings were electrodeposited from a bath using pulse current and modulated agitation. The total thickness of single layer and multilayer coatings was fixed at 5 μm and multilayer coatings with different modulation wavelengths and Cr to Ni thickness ratio were electrodeposited. Corrosion behavior of coatings was then studied by using potentiodynamic polarization test and electrochemical impedance spectroscopy in 0.1 M H2SO4. The results showed that Cr and Ni single layers had low corrosion resistance due to the presence of surface cracks and pores, respectively. On the other hand, optimized 20 nm Cr/50 nm Ni multilayer deposition significantly improved corrosion resistance. 相似文献
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50.
Directory-based and bus-based cache coherence schemes are defined and described. Directory-based schemes can be classified as centralized or distributed. Both categories support local caches to improve processor performance and reduce traffic in the interconnection. Schemes using presence flags, B pointers, and linked lists are discussed. Bus-based systems provide uniform memory access to all processors. This memory organization allows a simpler programming model, making it easier to develop new parallel applications or to move existing applications from a uniprocessor to a parallel system. Two architectural variations of bus-based systems are described: multiple-bus and hierarchical architectures 相似文献