A systematic review of state-of-the-art noise removal techniques in digital images

Digital Image processing is a subcategory of digital signal processing that lays emphasis on the study of processing techniques used for enhancement or restoration. De-noising of images corrupted with various types of noises falls into this category. De-noising is mainly performed to enhance the understandability of an affected image. Images captured with faulty equipment or being transmitted over long distances are highly prone to be depraved by impulse noise, so, various techniques are presented for removal of this noise from images. Each of the presented technique has its own merits and demerits. This paper presents a comprehensive comparative analysis of these techniques over a wide range of noise densities. All the filtering techniques are implemented in MATLAB and simulated with standard benchmark image data and qualitative metrics namely Peak Signal to Noise Ratio (PSNR) and Structural Similarity Index (SSIM) are evaluated and compared. Therefore, this paper presents a comprehensive comparative analysis of various state-of-the-art noise removal techniques.

     

Microarchitectural innovations: boosting microprocessor performancebeyond semiconductor technology scaling

Semiconductor technology scaling provides faster and more plentiful transistors to build microprocessors, and applications continue to drive the demand for more powerful microprocessors. Weaving the raw semiconductor material into a microprocessor that offers the performance needed by modern and future applications is the role of computer architecture. This paper overviews some of the microarchitectural techniques that empower modem high-performance microprocessors. The techniques are classified into: 1) techniques meant to increase the concurrency in instruction processing, while maintaining the appearance of sequential processing and 2) techniques that exploit program behavior. The first category includes pipelining, superscalar execution, out-of-order execution, register renaming, and techniques to overlap memory-accessing instructions. The second category includes memory hierarchies, branch predictors, trace caches, and memory-dependence predictors. The paper also discusses microarchitectural techniques likely to be used in future microprocessors, including data value speculation and instruction reuse, microarchitectures with multiple sequencers and thread-level speculation, and microarchitectural techniques for tackling the problems of power consumption and reliability     

A boolean spider monkey optimization based energy efficient clustering approach for WSNs

Wireless sensor network (WSN) consists of densely distributed nodes that are deployed to observe and react to events within the sensor field. In WSNs, energy management and network lifetime optimization are major issues in the designing of cluster-based routing protocols. Clustering is an efficient data gathering technique that effectively reduces the energy consumption by organizing nodes into groups. However, in clustering protocols, cluster heads (CHs) bear additional load for coordinating various activities within the cluster. Improper selection of CHs causes increased energy consumption and also degrades the performance of WSN. Therefore, proper CH selection and their load balancing using efficient routing protocol is a critical aspect for long run operation of WSN. Clustering a network with proper load balancing is an NP-hard problem. To solve such problems having vast search area, optimization algorithm is the preeminent possible solution. Spider monkey optimization (SMO) is a relatively new nature inspired evolutionary algorithm based on the foraging behaviour of spider monkeys. It has proved its worth for benchmark functions optimization and antenna design problems. In this paper, SMO based threshold-sensitive energy-efficient clustering protocol is proposed to prolong network lifetime with an intend to extend the stability period of the network. Dual-hop communication between CHs and BS is utilized to achieve load balancing of distant CHs and energy minimization. The results demonstrate that the proposed protocol significantly outperforms existing protocols in terms of energy consumption, system lifetime and stability period.     

Bacillus thuringiensis enzyme-digested delta endotoxin: effect on cultured insect cells

Cells from three insect cell lines responded to the enzyme-digested delta endotoxin of Bacillus thuringiensis with swelling, lysis, and vesicle formation. Sufficient toxin was taken up in 1 minute to cause half-maximal cell damage. Cytoxic activity was neutralized by specific antiserum to the endotoxin.     

Corrosion resistance of multilayer coatings of nanolayered Cr/Ni electrodeposited from Cr(III)-Ni(II) bath

In this study the corrosion resistance of chromium and nickel single layers and multilayer coatings of nanolayered Cr/Ni, electrodeposited from Cr(III)-Ni(II) baths on low carbon steel substrates, has been studied. The coatings were electrodeposited from a bath using pulse current and modulated agitation. The total thickness of single layer and multilayer coatings was fixed at 5 μm and multilayer coatings with different modulation wavelengths and Cr to Ni thickness ratio were electrodeposited. Corrosion behavior of coatings was then studied by using potentiodynamic polarization test and electrochemical impedance spectroscopy in 0.1 M H₂SO₄. The results showed that Cr and Ni single layers had low corrosion resistance due to the presence of surface cracks and pores, respectively. On the other hand, optimized 20 nm Cr/50 nm Ni multilayer deposition significantly improved corrosion resistance.     

Scalable shared-memory multiprocessor architectures

Directory-based and bus-based cache coherence schemes are defined and described. Directory-based schemes can be classified as centralized or distributed. Both categories support local caches to improve processor performance and reduce traffic in the interconnection. Schemes using presence flags, B pointers, and linked lists are discussed. Bus-based systems provide uniform memory access to all processors. This memory organization allows a simpler programming model, making it easier to develop new parallel applications or to move existing applications from a uniprocessor to a parallel system. Two architectural variations of bus-based systems are described: multiple-bus and hierarchical architectures