A Residue-to-Binary Converter for a New Five-Moduli Set

The efficiency of the residue number system (RNS) depends not only on the residue-to-binary converters but also the operand sizes and the modulus in each residue channel. Due to their special number theoretic properties, RNS with a moduli set consisting of moduli in the form of 2 ⁿplusmn1 is more attractive than those with other forms of moduli. In this paper, a new five-moduli set RNS {2ⁿ-1,2ⁿ,2ⁿ+1,2ⁿ+1-1,2 ^n-1-1} for even n is proposed. The new moduli set has a dynamic range of (5n-1) bits. It incorporates two additional moduli to the celebrated three-moduli set, {2ⁿ-1,2ⁿ,2ⁿ +1} with VLSI efficient implementations for both the binary-to-residue conversion and the residue arithmetic units. This extension increases the parallelism and reduces the size of each residue channel for a given dynamic range. The proposed residue-to-binary converter relies on the properties of an efficient residue-to-binary conversion algorithm for {2ⁿ-1,2ⁿ,2ⁿ+1,2ⁿ+1-1} and the mixed-radix conversion (MRC) technique for the two-moduli set RNS. The hardware implementation of the proposed residue-to-binary converter employs adders as the primitive operators. Besides, it can be easily pipelined to attain a high throughput rate     

Low-complex dynamic programming algorithm for hardware/software partitioning

A low-complex algorithm is proposed for the hardware/software partitioning. The proposed algorithm employs dynamic programming principles while accounting for communication delays. It is shown that the time complexity of the latest algorithm has been reduced from O(n²⋅A) to O(n⋅A), without increase in space complexity, for n code fragments and hardware area A.     

Rapid design of area-efficient custom instructions for reconfigurable embedded processing

RISPs (Reconfigurable Instruction Set Processors) are increasingly becoming popular as they can be customized to meet design constraints. However, existing instruction set customization methodologies do not lend well for mapping custom instructions on to commercial FPGA architectures. In this paper, we propose a design exploration framework that provides for rapid identification of a reduced set of profitable custom instructions and their area costs on commercial architectures without the need for time consuming hardware synthesis process. A novel clustering strategy is used to estimate the utilization of the LUT (Look-Up Table) based FPGAs for the chosen custom instructions. Our investigations show that the area costs computations using the proposed hardware estimation technique on 20 custom instructions are shown to be within 8% of those obtained using hardware synthesis. A systematic approach has been adopted to select the most profitable custom instruction candidates. Our investigations show that this leads to notable reduction in the number of custom instructions with only marginal degradation in performance. Simulations based on domain-specific application sets from the MiBench and MediaBench benchmark suites show that on average, more than 25% area utilization efficiency (performance/area) can be achieved with the proposed technique.     

Algorithmic aspects for multiple-choice hardware/software partitioning

Hardware–software partitioning (HW/SW) divides an application into software and hardware. It is one of the crucial steps in embedded system design. For a given task, hardware with different areas may provide different execution speeds due to the potential of parallel execution in hardware implementation. Thus, one task may have multiple-choice in hardware implementation according to the available hardware areas. Existing HW/SW partitioning approaches typically consider only a single implementation manner in hardware, overlooking the multiple-choice of hardware implementations. This paper presents a computing model to cater for the HW/SW partitioning problems with the multiple-choice implementation in hardware. An efficient heuristic algorithm is proposed to rapidly generate approximate solution, that is further refined by a tabu search algorithm also customized in this paper. Moreover, a dynamic programming algorithm is proposed for the exact solution of the relatively small problems. Extensive simulation results show that the approximate solutions are very close to the exact ones, and they can be refined by tabu search to the solutions with the error no more than 1.5% for all cases considered in this paper.     

Hardware-efficient schemes for logarithmic approximation and binary search with application to visibility graph construction

Visibility graphs constitute a useful data structure for environment representation in the context of robot path planning. A central element in the construction of the basic visibility graph and its variants is tangent determination. This letter presents new schemes and hardware designs for key elements in tangent construction and identification of obstructed tangents. The designs have been synthesized using Synopsys Design Compiler 2001.08-SP1, and results show they are appropriate for development of a cost-effective and efficient visibility graph generation system.     

Environment Modelling for Robot Navigation Using VLSI-Efficient Logarithmic Approximation Method

One of the major drawbacks of the visibility graph-based environment modelling process is its high computational complexity, particularly when the number of obstacles is large. In this paper, a logarithmic approximation based gradient computation method has been proposed to efficiently identify the farthest front vertices. It has been shown that the half-plane methods can be employed by examining only these farthest front vertices to rapidly identify the links that are obstructed by other objects. Novel techniques have been incorporated to substantially reduce the size of the look-up table required to implement the logarithmic approximation method. VLSI efficient architecture was then developed to demonstrate the viability of incorporating the visibility graph-based approach into a high-speed environment modelling process, which is well suited to dynamic robot navigation.     

Selecting profitable custom instructions for reconfigurable processors

Custom-instruction selection is an essential phase in instruction set extension for reconfigurable processors. It determines the most profitable custom-instruction candidates for implementing in the reconfigurable fabric of a reconfigurable processor. In this paper, a practical computing model is proposed for the custom-instruction selection problem that takes into account the area constraint of the reconfigurable fabric. Based on the new computing model, two heuristic algorithms and an exact algorithm are proposed. The first heuristic algorithm, denoted as HEA, dynamically assigns priorities to the custom instruction candidates and incorporates efficient strategies to select custom instructions with the highest priority. The second heuristic algorithm, denoted as TSA, employs an efficient tabu search algorithm to refine the results of HEA to near-optimal ones. Also, a branch-and-bound algorithm (BnB) is proposed to produce exact solutions for relatively small-sized problems or problems with stringent area-constraints. Experimental results show that HEA can produce more specific approximate solutions with a difference of only about 3% when compared to the optimal solutions produced by BnB. This difference is further reduced to about 0.6% by TSA. In addition, for large-sized problems where the exact algorithm becomes prohibitive, HEA and TSA can still produce solutions within reasonable time.     

Parallel reconfiguration algorithms for mesh-connected processor arrays

Effective fault tolerance techniques are essential for improving the reliability of multiprocessor systems. At the same time, fault tolerance must be achieved at high speed to meet the real-time constraints of embedded systems. While parallelism has often been exploited to increase performance, to the best of our knowledge, there has been no previously reported work on parallel reconfiguration of mesh-connected processor arrays with faults. This paper presents two parallel algorithms to accelerate reconfiguration of the processor arrays. The first algorithm reconfigures a host array in parallel in a multithreading manner. The threads in the parallel algorithm execute independently within a safe rerouting distance. The second algorithm is based on a divide-and-conquer approach to first generate the leftmost segments in parallel and then merge the segments in parallel. When compared to the conventional algorithm, simulation results from a large number of instances confirm that the proposed algorithms significantly accelerate the reconfiguration without loss of harvest.     

High-Speed Environment Representation Scheme for Dynamic Path Planning

This paper presents an efficient approach to represent the environment, which can be used to facilitate dynamic path planning in robot navigation systems. The environment is modelled by first defining a 'virtual rectangle' to represent an environment that avoids unwanted obstacles. The obstacles within the environment are then represented as convex polygons to generate the required visibility graph. The devised techniques lend well for hardware porting and thus highly suited to high-speed generation of the visibility graph. It has been demonstrated that efficient dynamic path planning can be realised by generating the 'virtual rectangle' on the fly such that only the environment needed to facilitate onward traversal can be identified. Finally, the proposed algorithms lend well for high-speed computations as they facilitate a high-degree of parallelism at the architecture level.     

An Internet application for on-line banking

The Internet explosion and the possibility of direct digital interaction with large numbers of home consumers presents tremendous opportunities, and challenges, to the financial services community. Today's providers must reckon with the Internet and on-line services, or potentially lose prime customers to new, nontraditional players. In this paper, the design and development details of an on-line banking (OLB) application for one of the banks in Singapore have been described. The implementation of OLB requires the creation of website, webpages and links to other related information. It further allows the users to submit a loan application for computing installments for repayment and other related information. Two of the popular languages of Internet have been used for the implementation of OLB. Due to proprietary nature of the application, certain implementation details are not provided in this paper.