Accelerating rotation of high-resolution images

Real-time image rotation is an essential operation in many application areas such as image processing, computer graphics and pattern recognition. Existing architectures that rely on CORDIC computations for trigonometric operations cause a severe bottleneck in high-throughput applications, especially where high-resolution images are involved. A novel hierarchical method that exploits the symmetrical characteristics of the image to accelerate the rotation of high-resolution images is presented. Investigations based on a 512times512 image show that the proposed method yields a speedup of ~20times for a mere 3% increase in area cost when compared with existing techniques. Moreover, the effect of hierarchy on the computational efficiency has been evaluated to provide for area-time flexibility. The proposed technique is highly scalable and significant performance gains are evident for very high-resolution images     

Power Efficient Sub-Array in Reconfigurable VLSI Meshes

Given an m×n mesh-connected VLSI array with some faulty elements, the reconfiguration problem is to find a maximum-sized fault-free sub-array under the row and column rerouting scheme. This problem has already been shown to be NP-complete. In this paper, new techniques are proposed, based on heuristic strategy, to minimize the number of switches required for the power efficient sub-array. Our algorithm shows that notable improvements in the reduction of the number of long interconnects could be realized in linear time and without sacrificing on the size of the sub-array. Simulations based on several random and clustered fault scenarios clearly reveal the superiority of the proposed techniques.     

New Model and Algorithm for Hardware/Software Partitioning

This paper focuses on the algorithmic aspects for the hardware/software （HW/SW） partitioning which searches a reasonable composition of hardware and software components which not only satisfies the constraint of hardware area but also optimizes the execution time. The computational model is extended so that all possible types of communications can be taken into account for the HW/SW partitioning. Also, a new dynamic programming algorithm is proposed on the basis of the computational model, in which source data, rather than speedup in previous work, of basic scheduling blocks are directly utilized to calculate the optimal solution. The proposed algorithm runs in O（n·A） for n code fragments and the available hardware area A. Simulation results show that the proposed algorithm solves the HW/SW partitioning without increase in running time, compared with the algorithm cited in the literature.     

Enhanced low-complexity pruning for corner detection

Low-complexity corner detection is essential for many real-time computer vision applications that need to be executed on low-cost/low-power embedded platforms such as robots. The widely used Shi–Tomasi and Harris corner detectors become prohibitive in such platforms due to their high computational complexity, which is attributed to the need to apply a complex corner measure on the entire image. In this paper, we introduce a novel and computationally efficient technique to accelerate the Shi–Tomasi and Harris corner detectors. The proposed technique consists of two steps. In the first step, the complex corner measure is replaced with simple approximations to quickly prune away non-corners. In the second step, the complex corner measure is applied to a small corner candidate set obtained after pruning. Evaluations using standard image benchmarks show that the proposed pruning technique achieves up to 75 % speedup on the Nios-II platform, while yielding corners with comparable or better accuracy than the conventional Shi–Tomasi and Harris detectors.     

Area-time efficient between-class variance module for adaptive segmentation process

Adaptive progressive thresholding (APT) has been shown to be an efficient method to segment the lumen region of endoscopic images. A pipelined architecture was previously proposed in an attempt to accelerate the conventional APT in hardware. A novel architecture for the between-class variance computations of APT is presented to minimise the severe bottleneck of the iterative loop in the APT process. The technique employs binary logarithm conversion to eliminate the computationally intensive dividers and reduce the complexity of the multipliers of the previous architecture. The proposed method employs a reconfigurable logarithmic computing unit, which can be configured to achieve a highly accurate between-class variance unit. It has been shown that the proposed approach leads to an area-time efficient FPGA implementation which is capable of a computation speed-up of /spl sim/2.75 times while occupying only one-sixth of the number of slices required by the previous approach.     

Single sided switching networks

A novel and simple architecture for realising single-sided, rearrangeably-nonblocking, N-port switching networks (N is a power of 2), that uses N/2 log (N/2) elements, together with an efficient routing algorithm with time complexity O(N log (N)) is presented. The networks also exhibit a useful measure of fault tolerance.<>     

Effect of pseudomonas lipase enzyme on the degradation of polycaprolactone/polycaprolactone-polyglycolide fiber blended nanocomposites

This study describes the interaction resulting from adding pseudomonas lipase (PS) enzyme to polycaprolactone-based composites designed for orthopedic applications. The biopolymer composite evaluated in this study consists of electrospun polycaprolactone (PCL)/polyglycolide (PGA) blended fibers impregnated with double stranded deoxyribonucleic acid wrapped single-walled carbon nanotubes encapsulated by a PCL matrix. PS enzyme was used to catalyze the degradation of PCL-based biocomposites. PCL present in the biocomposites showed considerable degradation in 4 weeks in the presence of the enzyme, exhibiting a contrast to hydrolytic degradation which lasts several years. PGA-consisting fibers degraded completely within one week of exposure to the enzyme.     

Scalable and modular memory-based systolic architectures for discrete Hartley transform

In this paper, we present a design framework for scalable memory-based implementation of the discrete Hartley transform (DHT) using simple and efficient systolic and systolic-like structures for short and prime transform lengths, as well as, for lengths 4 and 8. We have used the proposed short-length structures to construct highly modular architectures for higher transform lengths by a new prime-factor implementation approach. The structures proposed for the prime-factor DHT, interestingly, do not involve any transposition hardware/time. Besides, it is shown here that an N-point DHT can be computed efficiently from two (N/2)-point DHTs of its even- and odd-indexed input subsequences in a recursive manner using a ROM-based multiplication stage. Apart from flexibility of implementation, the proposed structures offer significantly lower area-time complexity compared with the existing structures. The proposed schemes of computation of the DHT can conveniently be scaled not only for higher transform lengths but also according to the hardware constraint or the throughput requirement of the application.     

Minimizing interconnect length on reconfigurable meshes

Shorter total interconnect and fewer switches in a processor array definitely lead to less capacitance, power dissipation and dynamic communication cost between the processing elements. This paper presents an algorithm to find a maximum logical array (MLA) that has shorter interconnect and fewer switches in a reconfigurable VLSI array with hard/soft faults. The proposed algorithm initially generates the middle (⌊k/2⌋ ^th ) logical column and then makes it nearly straight for the MLA with k logical columns. A dynamic programming approach is presented to compact other logical columns toward the middle logical column, resulting in a tightly-coupled MLA. In addition, the lower bound of the interconnect length of the MLA is proposed. Experimental results show that the resultant logical array is nearly optimal for the host array with large fault size, according to the proposed lower bound.     

Route computation in large road networks: a hierarchical approach

The optimal route between a given origin and destination needs to be computed in a fast and efficient manner in dynamic route guidance systems. Conventional routing algorithms have been found to be inadequate when applied directly to large road networks. Algorithms based on the concept of hierarchical abstraction make use of the knowledge about the road network to reduce search and provide near-optimal solutions. A generic procedure is presented for organising a given road network as a multiple-layer hierarchy. An efficient hierarchical routing algorithm is proposed, which breaks down the route search into a number of individual searches in small sub-networks. The algorithm incorporates a heuristic layer-switching technique to improve its performance without compromising the accuracy. The hierarchical routing algorithm was tested on the road network of Singapore and the solutions were found to be comparable to the optimal least-cost paths.