Minimizing interconnect length on reconfigurable meshes

Shorter total interconnect and fewer switches in a processor array definitely lead to less capacitance, power dissipation and dynamic communication cost between the processing elements. This paper presents an algorithm to find a maximum logical array (MLA) that has shorter interconnect and fewer switches in a reconfigurable VLSI array with hard/soft faults. The proposed algorithm initially generates the middle (⌊k/2⌋ ^th ) logical column and then makes it nearly straight for the MLA with k logical columns. A dynamic programming approach is presented to compact other logical columns toward the middle logical column, resulting in a tightly-coupled MLA. In addition, the lower bound of the interconnect length of the MLA is proposed. Experimental results show that the resultant logical array is nearly optimal for the host array with large fault size, according to the proposed lower bound.     

Route computation in large road networks: a hierarchical approach

The optimal route between a given origin and destination needs to be computed in a fast and efficient manner in dynamic route guidance systems. Conventional routing algorithms have been found to be inadequate when applied directly to large road networks. Algorithms based on the concept of hierarchical abstraction make use of the knowledge about the road network to reduce search and provide near-optimal solutions. A generic procedure is presented for organising a given road network as a multiple-layer hierarchy. An efficient hierarchical routing algorithm is proposed, which breaks down the route search into a number of individual searches in small sub-networks. The algorithm incorporates a heuristic layer-switching technique to improve its performance without compromising the accuracy. The hierarchical routing algorithm was tested on the road network of Singapore and the solutions were found to be comparable to the optimal least-cost paths.     

Exploiting Inherent Parallelisms for Accelerating Linear Hough Transform

Accelerating Hough transform in hardware has been of interest due its popularity in real-time capable image processing applications. In most existing linear Hough transform architectures, an m times medge map is serially read for processing, resulting in a total computation time of at least m² cycles. In this paper, we propose a novel parallel Hough transform computation method called the Additive Hough transform (AHT), wherein the image is divided using a k times k grid to reduce the total computation time by a factor of k². We have also proposed an efficient implementation of the AHT consisting of a look-up table (LUT) and two-operand adder arrays for every angle. Techniques to condense the LUT size have also been proposed to further reduce area utilization by as much as 50%. Our investigations based on employing an 8 times 8 grid shows a 1000 times speedup compared to existing architectures for a range of image sizes. Area-time trade-off analysis has been presented to demonstrate that the area-time product of the proposed AHT-based implementation is at least 43% lower than other implementations reported in the literature. We have also included and characterized a hierarchical addition step in order to generate a global accumulation space equivalent to that of the conventional HT. It is shown that the proposed implementation with the hierarchical addition step remains superior to other methods in terms of both performance and area-time product metrics. Finally, we show that the proposed solution is equally efficient when applied on rectangular images.     

弧焊过程神经网络模糊控制

提出一种将FLC与神经网络技术相结合的方法对钨极氩弧焊（GTAW）过程进行控制,它克服了模糊规则产生对专家的依赖及模糊集非自适应性的问题。隶属函数的自适应及模糊规则的自组织通过神经网络的自学习和竞争获得。该方法实现了弧焊过程中模糊规则的自动确定和隶属度函数在线调度。 以GTAW过程焊缝几何参数调节为对象,验证了算法的有效性。计算机仿真表明,采用该方法的系统性能有较大的提高。     

Algorithmic aspects of area-efficient hardware/software partitioning

Area efficiency is one of the major considerations in constraint aware hardware/software partitioning process. This paper focuses on the algorithmic aspects for hardware/software partitioning with the objective of minimizing area utilization under the constraints of execution time and power consumption. An efficient heuristic algorithm running in O(n log n) is proposed by extending the method devised for solving the 0-1 knapsack problem. Also, an exact algorithm based on dynamic programming is proposed to produce the optimal solution for small-sized problems. Simulation results show that the proposed heuristic algorithm yields very good approximate solutions while dramatically reducing the execution time.