Three-dimensional large-screen display with reflection-mode spatial light modulators and a single-projection optical system: analysis of a retardation-modulation method

A stereoscopic projector with polarized glasses is proposed that consists of spatial light modulators (SLM's) that control the retardation of projected light, a polarization beam splitter (PBS), and single-projection optics. This display's features include a three-dimensional (3-D) image display with a single projector and half the size and the power consumption of a conventional 3-D projector. Analysis shows that the cross talk and the extinction ratio of this system depend strongly on the polarized light-separation characteristics of the PBS, the light output, and the extinction ratio of the SLM's. A double-PBS method that drastically improves 3-D image quality is also discussed.     

Global color impressions of multicolored textured patterns with equal unique hue elements

A global color impression from a multicolored textured pattern can be identified. It is not clear, however, how such a single color impression can be determined from the elemental colors of the multicolored textured pattern. To investigate this question, two hypotheses were evaluated. The first hypothesis is that a single color impression is determined by the colorimetric average of the elemental colors in the textured pattern (colorimetric average hypothesis). The second hypothesis is that the impression is influenced by the color appearances of the elemental colors in the textured pattern (color appearance hypothesis). Using an asymmetrical color matching method, the authors obtained single color impressions for random‐dot textured patterns consisting of two colors with the same unique hue and brightness but each with a different saturation. Our results showed that the matched colors were not located on the line connecting the two elemental colors of the pattern, but rather were on the curved unique hue loci line. Furthermore, the chromaticities of the matches shifted toward a higher saturation than the colorimetric averages. These results support the color appearance hypothesis and suggest that a single color impression from a multicolored textured pattern is determined by a mechanism that integrates the color appearances, i.e., hue, saturation, and brightness (or lightness), of the elemental colors in the pattern. In addition, it seems that the integration of the color appearances is not a simple process, because the apparent saturation of the color impression was higher than that of the colorimetric average and the average of the chromaticities of the colors in the pattern. © 2007 Wiley Periodicals, Inc. Col Res Appl, 32, 267–277, 2007     

Quantum Field Theoretical Description of Dynamical Instability of Trapped Bose–Einstein Condensates

The Bogoliubov–de Gennes equations are used for a number of theoretical works on the trapped Bose–Einstein condensates. We consider the case in which these equations have complex eigenvalues. We give the complete set including a pair of complex modes whose eigenvalues are complex conjugate to each other. The expansion of the quantum fields which represent neutral atoms in terms of the complete set brings about the operators associated with the complex modes, which are simply neither bosonic nor fermionic ones. The eigenstate of the Hamiltonian is given. Introducing the notion of the physical states, we discuss the instability of the condensates in the context of Kubo’s linear response theory.     

A full bit prefetch DRAM sensing circuit

A DRAM sensing circuit that achieves both a fast RAS access time and a high-bandwidth burst operation is proposed. For the data burst capability of synchronous DRAM's, 256-bit-long data I/O lines are divided into eight segments. A small local latch is provided for each segment of 32 bit-line pairs to prefetch eight data out of the 256 sense amplifiers. A local buffer is connected to eight local latches through selection switches. Burst read operations, up to eight bits, are done by activating selection switches and the local buffer serially. Besides this prefetch capability, the segmented data I/O line results in very small capacitance, only 0.09 pF. The sensing scheme uses nMOS bit switches and a full Vdd precharge voltage for bit and segmented data I/O lines. Then, after sense amplifiers are turned on, only low-going bit lines are connected to the segmented data I/O lines without any voltage disturbance because of the small capacitance. The proposed circuit, therefore, realizes a high-speed RAS access, which is 16 ns faster than a conventional DRAM. A circuit layout design based on a 0.5-μm design rule shows no area impact     

An eight-bit prefetch circuit for high-bandwidth DRAM's

A low-power and area-efficient data path circuit for high-bandwidth DRAMs is described. For fast burst read operations, eight data per data I/O are stored in local latches placed close to sense amplifiers. As implemented in a 16-Mb synchronous DRAM (SDRAM), this 8-b prefetch circuit allows an early precharge command and a fast access time because it provides low-capacitance data lines for segmented bit-line pairs. At a column address strobe (CAS) latency of two and a burst length of four, the SDRAM demonstrates 100-MHz seamless read operations from different row addresses, because the row precharge and read access latencies are hidden during the burst cycles. The layout of the prefetch circuit is not limited by the bit-line pitch, and data path circuits are connected by a second-metal layer over the memory cells. As a result, a small chip size of 99.98 mm² is attained. Low-capacitance data lines and small local latches result in low active power. In a 100-MHz full-page burst mode, the SDRAM with a 1 M×16-b configuration dissipates 60 mA at 3.6 V     

Biomechanics of rising from a chair and walking in pregnant women

The present study aimed to assess the changes in the pattern of rising from a chair and walking forward as pregnancy progressed. Twelve pregnant women and 10 nulliparous women were included in this study. Participants were videotaped with a digital video camera in the sagittal plane, and the coordinates of the markers attached to the subjects were identified using image analysis software. The peak trunk-flexion angle in pregnant women during rising was smaller, but the hip-extension angle during the stance phase was larger than in controls. Also, the peak horizontal and vertical velocities of the center of mass were lower, and appeared earlier, in pregnant women than in controls. During rising, pregnant women dampened the propulsion attributable to increased uterus volume, and they enhanced the forward propulsion at gait initiation. To ensure safe motion, pregnant women should not initiate gait until reaching a stable standing position after rising.     

Neutron production rate and plasma characteristics of spherically convergent beam fusion

Experimental and simulation results of a spherical glow discharge for a portable neutron source are presented. The experimental device is a 45‐cm‐diameter, 31‐cm‐high stainless‐steel cylindrical chamber, in which a spherical mesh‐type anode 30 cm in diameter is installed. The spherical grid cathode consists of 2.0‐mm‐diameter stainless‐steel wire, which is made into an open spherical grid of 5‐cm diameter. The system is maintained at a constant pressure of 1 to 15 mTorr by feeding hydrogen or deuterium gas. The basic characteristics of breakdown voltages versus pressure and electrostatic potential profiles were measured for hydrogen discharge. Using deuterium, a steady‐state neutron production of 10⁴ s^–1 was observed at a discharge of 40 kV, 2 mA. Motions of ions and electrons in the device were simulated by using a particle code, which is one‐dimensional in coordinate system and two‐dimensional in velocity space. It was confirmed by both the measurement and simulation that a virtual anode is formed in the central part inside the grid cathode. © 2001 Scripta Technica, Electr Eng Jpn, 135(2): 1–8, 2001     

DRAM macros for ASIC chips

DRAM macros in 4-Mb (0.8-μm) and 16-Mb (0.5-μm) DRAM process technology generations have been developed for CMOS ASIC applications. The macros use the same area efficient one transistor trench cells as 4-Mb (SPT cell) and 16-R Mb (MINT cell) DRAM products. It is shown that the trench cells with capacitor plates by the grounded substrate are ideal structures as embedded DRAM's. The trench cells built entirely under the silicon surface allow cost effective DRAM and CMOS logic merged process technologies. In the 0.8-μm rule, the DRAM macro has a 32-K×9-b configuration in a silicon area of 1.7×5.0 mm² . It achieves a 27-ns access and a 50-ns cycle times. The other DRAM macro in the 0.5-μm technology is organized in 64 K×18 b. It has a macro area of 2.1×4.9 mm and demonstrated a 23-ns access and a 40-ns cycle times. Small densities and multiple bit data configurations provide a flexibility to ASIC designs and a wide variety of application capabilities. Multiple uses of the DRAM macros bring significant performance leverages to ASIC chips because of the wide data bus and the fast access and cycle times. A data rate more than 1.3 Gb/s is possible by a single chip. Some examples of actual DRAM macro embedded ASIC chips are shown