Implementation of a self-timed segmented bus

We propose an asynchronous structure for implementation on a SoC. An intersegment topological arrangement preserves parallelization and, through a so-called central arbiter, efficiently organizes communication with high signaling speed in the proposed structure. Researchers proposed the concept of segmenting buses primarily for multicomputer architectures. More recent approaches address on-chip implementation of segmented buses. We present an asynchronous segmented-bus architecture targeted for the modular design of high-performance SoC applications. The structure not only enables faster operation than a conventional bus system but also offers lower power consumption per transferred data item. This is possible because segmentation is realized in such a way that the majority of data transfers in the system are intrasegment transactions on relatively short wires with low or moderate capacitive loads.     

A Distributed State Estimator Utilizing Synchronized Phasor Measurements

With the creation of balancing authorities by the North American Reliability Council that span large portions of the North American interconnection, and stringent requirements for real time monitoring of power system evolution, faster and more accurate state estimation algorithms that can efficiently handle systems of very large sizes are needed in the present environment. This paper presents a distributed state estimation algorithm suitable for large-scale power systems. Synchronized phasor measurements are applied to aggregate the voltage phase angles of each decomposed subsystem in the distributed state estimation solution. The aggregated state estimation solution is obtained from the distributed solution using a sensitivity analysis based update at chosen boundary buses. Placement of synchronized phasor measurements in the decomposed subsystems is also investigated in this paper. Test results on the IEEE 118-bus test bed are provided     

Low-Power VLSI Implementation of the Inner Receiver for OFDM-Based WLAN Systems

In this paper, we propose low-power designs for the synchronizer and channel estimator units of the Inner Receiver in wireless local area network systems. The objective of the work is the optimization, with respect to power, area, and latency, of both the signal processing algorithms themselves and their implementation. Novel circuit design strategies have been employed to realize optimal hardware and power efficient architectures for the fast Fourier transform, arc tangent computation unit, numerically controlled oscillator, and the decimation filters. The use of multiple clock domains and clock gating reduces the power consumption further. These blocks have been integrated into an experimental digital baseband processor for the IEEE 802.11a standard implemented in the 0.25mum- 5-metal layer BiCMOS technology from Institute for High Performance Microelectronics.     

The hot blow forming of AZ31 Mg sheet: Formability assessment and application development

The hot blow forming of magnesium sheet offers significant opportunity for forming complex, lightweight parts for automotive applications. This paper characterizes the elevated-temperature formability of AZ31 magnesium sheet materials and the effect of processing conditions on the performance of these materials. In addition, magnesium sheet application development at General Motors Corporation is reviewed.     

Diagnosis and Consulting for Control Network Performance Engineering of CSMA-Based Networks

Network performance engineering can verify the design and dimensioning of large-scale control networks like CSMA-based building automation networks. It combines performance analysis with diagnosis methods to evaluate the network utilization and to detect design errors before installation and can therewith save the expenses of overdimensioning and redesign. This paper will develop a diagnosis model based on fault trees that is able to use the huge amount of performance analysis results to identify design errors and analyze their coherences. This enables not only a fast tracing back of fault causes and the derivation of solutions; it can also visualize the fault coherence to the user and help him to understand his design. Additional consulting tools implement best practice strategies, to support the user in parameterization.     

Simulation of Strength Distribution in Ground Ceramics by Incorporating Residual Stress Effect

Strength of ground ceramics may be affected by residual stress as well as surface flaws induced by grinding. Strength prediction for ground ceramics is convenient for mechanical design of ceramic components. In this article, a numerical procedure based on fracture mechanics was proposed to estimate strength distribution of ground ceramics by considering grinding-induced residual stress. Bending strength and residual stress of ground ceramics were measured for three grinding-conditions. By comparison of simulated results with experimental ones, it was revealed that strength characteristics in experiments were well simulated by using the proposed procedure.     

Study of thermal effects and self-heating phenomena in planar power SOI MOS transistors

Heat removal problems, thermal effects, and self-heating phenomena occurring during operation of planar power SOI MOS transistors are considered. Using device-technological simulating methods, the transistor characteristics and safe operation range were studied. It was shown that limitations of the safe operation range are mostly associated with structure self-heating rather than with the parasitic bipolar transistor.     

Robust Distributed Source Coding

We consider a distributed source coding system in which several observations must be encoded separately and communicated to the decoder by using limited transmission rate. We introduce a robust distributed coding scheme which flexibly trades off between system robustness and compression efficiency. The optimality of this coding scheme is proved for various special cases.