Continuous phase quadrature phase shift keyed signaling techniquewith coding

A continuous phase quadrature phase shift keyed (CPQPSK) modulation technique is presented. This method utilizes a conventional QPSK modulator and a phase trajectory converter to approximate M=4, h=1/4 continuous phase signal and allows low cost, low complexity, and high rate (>1 Gbit/s) CPM modem implementation for bandwidth efficient transmission through nonlinear satellite channels. Using a communications analysis computer program it has been found that CPQPSK has 99 percent out-of-band power of 0.8R (MSK has 99 percent out-of-band power of 1.2 R where R is defined as bit rate), continuous phase trajectories, and nearly constant envelope amplitude. Simulation of realistic hardware designs indicate that the CPQPSK will require an Eb/No of 14 dB to achieve a bit error rate (BER) of 10^-6. Forward error correcting techniques using block codes with an overhead of 10 percent indicate that the Eb/No requirements can be reduced to 11.2 dB for 10^-6 BER     

A comparison between the axial flux and the radial flux structures for PM synchronous motors

The aim of this paper is the comparison of the axial flux (AF) structures versus the conventional radial flux (RF) structures for permanent-magnet synchronous motors. The comparison procedure is based on simple thermal considerations. Two motor typologies are chosen and compared in terms of delivered electromagnetic torque. The comparison is developed for different motor dimensions and the pole number influence is put into evidence. The paper reports the complete comparison procedure and the related results analysis. The obtained results show that, when the axial length is very short and the pole number is high, the AF motors can be an attractive alternative to the conventional RF solutions.     

Half-bridge inverter using 4H-SiC gate turn-off thyristors

This paper reports on the first demonstration of a half-bridge power inverter constructed from silicon carbide gate turn-off thyristors (GTOs) operated in the conventional GTO mode. This circuit was characterized with input bus voltages of up to 600 VDC and 2 A (peak current density of 540 A/cm²) with resistive loads using a pulse-width modulated switching frequency of 2 kHz. We discuss the implications of the thyristor's electrical characteristics and the circuit topology on the overall operation of the half-bridge circuit. This work has determined the conservative critical rate of rise value of the off-state voltage to be 200 V/μs in these devices     

Interactions of electron beams with surfaces of MgO crystals

The strong interaction of electrons with the flat surfaces of small crystals has been investigated by high resolution CTEM and STEM instruments. When cubic crystals of MgO smoke with edges 20–300 nm are oriented so that the ?001? or ?011? zone axis is parallel to the optical axis, then two kinds of external fringes are observed at (100) surfaces. One kind is parallel to the surface, having spacings up to 0.4 nm. These are caused by interference among the electron channelled along the surface. Fresnel-diffracted ones and the remnant of the incident beam. Fringes of the other kind, which appear as fine structure in the first kind of fringes, are perpendicular to the crystal edge. When an electron beam is parallel to the ?011? axis, the second kind of fringe, whose spacing is 0.3 nm corresponding to d₀₁₁, shows the difference of the surface potential between magnesium atoms and oxygen atoms. Selected area diffraction patterns and microdiffraction patterns also show the same periodicities as in the two kinds of fringes. Simulated images, using the scattering amplitudes for ions, are compared with observations.     

Effect of facet coatings on far fields of semiconductor lasers

A theoretical expression is derived for the far fields of semiconductor lasers with coated facets. It is shown that the far fields are different for uncoated, antireflection-coated and high-reflection-coated lasers. The correction factor for the far fields is shown to depend on the transmission coefficient of the facets.     

Incremental transmission loss allocation under pool dispatch

Incremental transmission loss analysis has been used for decades, but recent interest in its application to loss allocation calls for new in-depth results. This paper demonstrates that, for incremental methods to be applied correctly in loss allocation, it is first necessary to specify the load distribution and loss supply strategies. Incremental loss allocation among bus power injections is shown to be arbitrary and, therefore, open to challenge as discriminatory. Loss allocation is possible among incremental loads and/or generators, but the proportion of the total losses assigned to either one is arbitrary. Unique, nonarbitrary incremental loss allocations are however possible among the "equivalent" incremental bilateral exchanges between generators and loads. From these basic components it is possible then to calculate the allocation among generators or loads in any specified proportion. The main results, although developed initially for small increments, are extended to large variations. Finally, a general incremental loss allocation algorithm is developed and tested     

Crisis phenomena upon evaporation in grid capillary and porous coatings and arterial structures of heat pipes

The article presents the results of experimental investigations of critical (limit) heat fluxes upon evaporation on porous coatings, and it substantiates the physical model of the process.Translated from Inzhenerno-Fizicheskii Zhurnal, Vol. 49, No. 4, pp. 607–614, October, 1985.     

Implementation of a self-timed segmented bus

We propose an asynchronous structure for implementation on a SoC. An intersegment topological arrangement preserves parallelization and, through a so-called central arbiter, efficiently organizes communication with high signaling speed in the proposed structure. Researchers proposed the concept of segmenting buses primarily for multicomputer architectures. More recent approaches address on-chip implementation of segmented buses. We present an asynchronous segmented-bus architecture targeted for the modular design of high-performance SoC applications. The structure not only enables faster operation than a conventional bus system but also offers lower power consumption per transferred data item. This is possible because segmentation is realized in such a way that the majority of data transfers in the system are intrasegment transactions on relatively short wires with low or moderate capacitive loads.