A Scheduling Framework for UWB & Cellular Networks

The max-min fair scheduling problem in wireless ad-hoc networks is a non-convex optimization problem. A general framework is presented for this optimization problem and analyzed to obtain a dual problem, which involves solving a series of optimization sub-problems. In the limit of infinite bandwidth ( ), the scheduling solution reduces to simultaneous transmission (spread spectrum) on all links (Negi and Rajeswaran, INFOCOM '04 (March 2004)). This motivates the analysis of the scheduling problem in the Ultra Wide Band (UWB) regime ( , but finite), a model for certain practical radios. A quadratic (in 1/W) lower bound to the single link capacity function is developed, which simplifies the dual sub-problem to a quadratic optimization (Negi and Rajeswaran, GLOBECOM '04, (Dec. 2004)). The solution to this sub-problem is then obtained under both total power and power spectral density constraints. This solution is utilized to iteratively construct the schedule (sub-band sizes) and power allocation, thus optimally solving the UWB max-min fair scheduling problem, to within any desired precision. Simulations on medium sized networks demonstrate the excellent performance of this scheme. A cellular architecture (not necessarily UWB) may also be considered in this framework. It is proved that Frequency Division Multiple Access is the optimal scheduling for a multi-band cellular architecture. This work was supported in part by the National Science Foundation under Career award 0347455. Arjunan Rajeswaran received his Masters degree in Electrical and Computer Engineering from Carnegie Mellon University in 2003. Since August 2003, he has been pursuing his doctoral research at Carnegie Mellon. His reserach interests lie in the area of wireless networks. His focus is in the application of information and communication theoretic tools towards wireless network design. Several IEEE publications reflect his curent research on Medium Access Control design and performance. Arjunan received the best student paper award at IEEE/ACM Broadnets 2004. Gyouhwan Kim received his B.S. and M.S. degree in Electronic Engineering from Sogang University in Korea, in 1994 and 1996, respectively. Since 1996, he has been working in the CDMA cellular system development team in Samsung Electronics. Currently, he is also working toward the Ph.D degree in the Department of Electrical and Computer Engineering at Carnegie Mellon University. His main research interests are in wireless networks and communication theory. Rohit Negi received the B.Tech. degree in Electrical Engineering from the Indian Institute of Technology, Bombay, India in 1995. He received the M.S. and Ph.D. degrees from Stanford University, CA, USA, in 1996 and 2000 respectively, both in Electrical Engineering. He has received the President of India Gold medal in 1995. Since 2000, he has been with the Electrical and Computer Engineering department at Carnegie Mellon University, Pittsburgh, PA, USA, where he is an Assistant Professor. His research interests include signal processing, coding for communications systems, information theory, networking, cross-layer optimization and sensor networks.     

Development of intracranial brain-computer interface system using non-motor brain area for series of motor functions

An intracranial brain-computer interface (BCI) system using the neuronal activity of a non-motor brain area to fulfil a series of motor functions has been developed. The presented BCI system encodes a series of motor functions into a small number of neuronal units of the primary somatosensory cortex of a rat and generates real-time command signals to control a machine according to the animal's motor intentions. The results of this study demonstrate the practical usability of the BCI system using a non-motor brain area in the field of rehabilitation.     

A 20-GHz phase-locked loop for 40-gb/s serializing transmitter in 0.13-/spl mu/m CMOS

A 20-GHz phase-locked loop with 4.9 ps/sub pp//0.65 ps/sub rms/ jitter and -113.5 dBc/Hz phase noise at 10-MHz offset is presented. A half-duty sampled-feedforward loop filter that simply replaces the resistor with a switch and an inverter suppresses the reference spur down to -44.0 dBc. A design iteration procedure is outlined that minimizes the phase noise of a negative-g/sub m/ oscillator with a coupled microstrip resonator. Static frequency dividers made of pulsed latches operate faster than those made of flip-flops and achieve near 2:1 frequency range. The phase-locked loop fabricated in a 0.13-/spl mu/m CMOS operates from 17.6 to 19.4GHz and dissipates 480mW.     

Joint data rate and power allocation for lifetime maximization in interference limited ad hoc networks

In this paper, we consider the following problem in the wireless ad hoc network: Given a set of paths between source and destination, how to divide the data flow among the paths and how to control the transmission rates, times, and powers of the individual links in order to maximize the operation time of the worst network node. If all nodes are of equal importance, the operation time of the worst node is also the lifetime of the network. By solving the problem, our aim is to investigate how the network lifetime is affected by link conditions such as the maximum transmission power of a node and the peak data rate of a link. For the purpose, we start from a system model that incorporates the carrier to interference ratio (CIR) into a variable data rate of a link. With this, we can develop an iterative algorithm for the lifetime maximization, which resembles to the distributed power control in cellular systems. Numerical examples on the iterative algorithm are included to illustrate the network lifetime as a function of the maximum transmission power and the peak data rate.     

TiN and TaN diffusion barriers in copper interconnect technology: Towards a consistent testing methodology

The present status of work on diffussion barriers for copper in multilevel interconnects is surveyed briefly, with particular emphasis on TiN and TaN, and silicon dioxide as the interlayer dielectric. New results are presented for these materials, combining thermal annealing and bias temperature stress testing. With both stress methods, various testing conditions are compared using capacitance-vs-voltage (C-V) and leakage current-vs-voltage (I-V) measurements to characterize the stressed samples. From an evaluation of these data and a comparison with other testing approaches, conditions for a consistent testing methodology of barrier reliability are outlined.     

Fiber-optic sensor array based on Sagnac interferometer with stablephase bias

We propose and experimentally demonstrate a novel fiber sensor array based on a Sagnac interferometer with very simple electronic signal processing. A stable quadrature phase bias was obtained using a phase modulator, and the polarization-induced signal fading was suppressed by using a depolarizer and a broad-band source. A phase sensitivity of about 4.0 μrad_rms/√Hz at 5 kHz was obtained using a two-sensor array     

Fabrication of laser-annealed poly-TFT by forming aSi1-xGex thermal barrier

Germanium is ion-implanted deeply into the bottom of a Si film before excimer laser annealing begins. During the solidification step, the implanted Ges form a high thermal resistive Si_1-xGe_x alloy, which reduces the thermal extraction rate of laser energy and the grain growth rate. Laterally larger but double-stacked grains were achieved with a higher Ge implant dose and a slower grain growth. The performance of fabricated poly-TFTs has been enhanced with a Ge 5×10¹⁵/cm² at 80 keV implant but deteriorated at a higher dose. We attribute this enhancement to a laterally enlarged grain and show that the performance of TFT is deteriorated more dominantly by other Ge-related factors than by surface roughening and Ge-induced defect creation     

A 1.8-GHz self-calibrated phase-locked loop with precise I/Qmatching

This paper describes a 1.8-GHz self-calibrated phase-locked loop (PLL) implemented in 0.35-μm CMOS technology. The PLL operates as an edge-combining type fractional-N frequency synthesizer using multiphase clock signals from a ring-type voltage-controlled oscillator (VCO). A self-calibration circuit in the PLL continuously adjusts delay mismatches among delay cells in the ring oscillator, eliminating the fractional spur commonly found in an edge-combing fractional divider due to the delay mismatches. With the calibration loop, the fractional spurs caused by the delay mismatches are reduced to -55 dBc, and the corresponding maximum phase offsets between the multiphase signals is less than 0.20. The frequency synthesizer PLL operates from 1.7 to 1.9 GHz and the closed-loop phase noise is -105 dBc/Hz at 100-kHz offset from the carrier. The overall circuit consumes 20 mA from a 3.0-V power supply     

Modal MRTD approaches for the efficient analysis of waveguidediscontinuities

This paper, the multi-resolution time-domain (MRTD) technique is applied to the waveguide discontinuity problem for fast-scattering parameter computation. To improve the computational efficiency, both three-dimensional (3-D) waveguide regions, including discontinuities, and one dimensional (1-D) homogeneous waveguide region, terminated with the modal absorbing boundary condition (ABC), are simulated in the wavelet domain with the mode composition/expansion algorithm from the modal analysis. A WG-90 rectangular waveguide with a thick asymmetric iris is analyzed and the numerical results are compared with conventional finite-difference time-domain (FDTD) results and mode-matching results     

Latch Applicator for Efficient Delivery of Dissolving Microneedles Based on Rapid Release of Elastic Strain Energy by Thumb Force (Adv. Funct. Mater. 11/2023)

Dissolving microneedle (DMN) is an attractive alternative to parenteral and enteral drug administration owing to its painless self-administration and safety due to non-generation of medical waste. For reproducible and efficient DMN administration, various DMN application methods, such as weights, springs, and electromagnetic devices, have been studied. However, these applicators have complex structures that are complicated to use and high production costs. In this study, a latch applicator that consists of only simple plastic parts and operates via thumb force without any external complex device is developed. Protrusion-shaped latches and impact distances are designed to accumulate thumb force energy through elastic deformation and to control impact velocity. The optimized latch applicator with a pressing force of 25 N and an impact velocity of 5.9 m s⁻¹ fully inserts the drug-loaded tip of the two-layered DMN into the skin. In an ovalbumin immunization test, DMN with the latch applicator shows a significantly higher IgG antibody production rate than that of intramuscular injection. The latch applicator, which provides effective DMN insertion and a competitive price compared with conventional syringes, has great potential to improve delivery of drugs, including vaccines.