A 9‐Bit 80‐MS/s CMOS Pipelined Folding A/D Converter with an Offset Canceling Technique

A 9‐bit 80‐MS/s CMOS pipelined folding analog‐to‐digital converter employing offset‐canceled preamplifiers and a subranging scheme is proposed to extend the resolution of a folding architecture. A fully differential dc‐decoupled structure achieves high linearity in circuit design. The measured differential nonlinearity and integral nonlinearity of the prototype are ×0.6 LSB and ×1.6 LSB, respectively.     

Well‐Defined Functional Linear Aliphatic Diblock Copolyethers: A Versatile Linear Aliphatic Polyether Platform for Selective Functionalizations and Various Nanostructures

Low‐temperature anionic ring‐opening homopolymerizations and copolymerizations of two glycidol derivatives (allyl glycidyl ether (AGE) and ethoxyethyl glycidyl ether (EEGE)) are studied using a metal‐free catalyst system, 3‐phenyl‐1‐propanol (PPA) (an initiator) and 1‐tert‐butyl‐4,4,4‐tris(dimethylamino)‐2,2‐bis[tris‐(dimethylamino)phosphoranylidenamino]‐2Λ⁵,4Λ⁵‐catenadi(phosphazene) (t‐Bu‐P₄) (a promoter) in order to obtain well‐defined functional linear polyethers and diblock copolymers. With the aid of the catalyst system, AGE is found to successfully undergo anionic ring‐opening polymerization (ROP) even at room temperature (low reaction temperature) without any side reactions, producing well‐defined linear AGE‐homopolymer in a unimodal narrow molecular weight distribution. Under the same conditions, EEGE also undergoes polymerization, producing a linear EEGE‐homopolymer in a unimodal narrow molecular‐weight distribution. In this case, however, a side reaction (i.e., chain‐transfer reaction) is found to occur at low levels during the early stages of polymerization. The chemical properties of the monomers in the context of the homopolymerization reactions are considered in the design of a protocol used to synthesize well‐defined linear diblock copolyethers with a variety of compositions. The approach, anionic polymerization via the sequential step feed of AGE and EEGE as the first and second monomers, is found to be free from side reactions at room temperature. Each block of the obtained linear diblock copolymers undergoes selective deprotection to permit further chemical modification for selective functionalization. In addition, thermal properties and structures of the polymers and their post‐modification products are examined. Overall, this study demonstrates that a low‐temperature metal‐free anionic ROP using the PPA/t‐Bu‐P₄ catalyst system is suitable for the production of well‐defined linear AGE‐homopolymers and their diblock copolymers with the EEGE monomer, which are versatile and selectively functionalizable linear aliphatic polyether platforms for a variety of post‐modifications, nanostructures, and their applications.     

Chip warpage model for reliability prediction of delamination failures

A new experimental method to predict reliability for ACA type packages under temperature cycling is developed and proposed. The method introduces a new damage parameter that can be easily measured by experiment. It is proved that the linear elastic parameter, dw/dT which represents the rate of change of chip warpage with respect to temperature, efficiently reflects the common failure mechanism of ACA type packages, the interfacial delamination between the chip and the adhesive. It is demonstrated, both experimentally and numerically, that the size of delamination affects the warpage behavior of the chip. The dw/dT of the chip is monitored in real time using laser interferometers under thermal fatigue cycles up to 3000. The gradual decrease in warpage due to progressive increase in delamination is clearly emerged. As a result, a reliability curve that can predict the size of delamination and remained life is obtained. The new long-term reliability prediction method developed in this study can be applied to various advanced packages, e.g. underfilled flip–chip or TSV stacked chip packages, that embrace interfacial delamination as primary failure mode.     

Characteristics of solderable electrically conductive adhesives (ECAs) for electronic packaging

This study investigated the effect of the viscosity of the ECAs using a low-melting-point alloy (LMPA) filler on its bonding characteristics. The curing behaviors of the ECAs were determined using Differential Scanning Calorimetry (DSC), and ECA temperature-dependant viscosity characteristics were observed using a torsional parallel rheometer. The wetting test was conducted to investigate the reduction capability of ECAs and the flow-coalescence-wetting behavior of the LMPAs in ECAs. Electrical and mechanical properties were determined and compared to those with commercial ECAs and eutectic tin/lead (Sn/Pb) solder. In the metallurgically interconnected Quad Flat Package (QFP) joint, a typical scallop-type Cu–Sn intermetallic compound (IMC) layer formed at the upper SnBi/Cu interface after curing process. On the other hand, a (Cu, Ni)₆Sn₅ IMC layer formed on the SnBi/ENIG interface. In addition, the fracture surface exhibited by cleavage fracture mode and the fracture was propagated along the Cu–Sn IMC/SnBi interface. The extremely low-level viscosity of ECAs had a significant influence on the flow-coalescence-wetting behavior of the LMPAs in ECAs and also on the interconnection properties. Stable interconnected assemblies showed good electrical and mechanical properties.     

Soluble processed low-voltage and high efficiency blue phosphorescent organic light-emitting devices using small molecule host systems

We report low voltage driving and highly efficient blue phosphorescence organic light emitting diodes (PHOLEDs) fabricated by soluble process. A soluble small molecule mixed host system consisting of hole transporting 4,4’,4’’ tris(N-carbazolyl)triphenylamine (TCTA) and bipolar carrier transporting 2,6-bis(3-(carbazol-9-yl)phenyl)pyridine (26DCzPPy) exhibits high solubility with smooth surface properties. Moreover, this small molecule host shows the smoothest morphological property similar to a vacuum deposited amorphous film. A low driving voltage of 5.4 V at 1000 cd/m² and maximum external quantum efficiency 14.6% obtained in the solution processed blue PHOLEDs are useful for large area low cost manufacturing.     

Base station location in a cellular CDMA system

We consider a cellular CDMA system in which blocking is enforced when the relative interference exceeds a certain threshold level. This paper addresses a radio network design problem in such a CDMA system. Given the data of call‐traffic distributed over the service area and potential sites of base stations, the objective of the problem is to locate base stations so as to minimize the associated cost for establishing base stations while keeping the probability of blocking under control. We develop an efficient algorithm for solving the design problem. Computational experiments with real‐world data are conducted to show both the efficiency and the practicality of the proposed design method. This revised version was published online in August 2006 with corrections to the Cover Date.     

Fabrication of polymeric large-core waveguides for opticalinterconnects using a rubber molding process

Polymeric large-core (47 μm×41 μm) optical waveguides for optical interconnects have been fabricated by using a rubber molding process. For low-cost low-loss large-core waveguides, our newly developed thick-photoresist patterning process is used for a master fabrication. Also a low-loss thermocurable polymer, perfluorocyclobutane (PFCB), is used in fabricating optical waveguides by rubber molding for the first time. The propagation loss is measured to be 0.4 dB/cm at the wavelength of 1.3 μm, and 0.7 dB/cm at the wavelength of 1.55 μm     

A new on-chip interconnect crosstalk model and experimentalverification for CMOS VLSI circuit design

A new, simple closed-form crosstalk model is proposed. The model is based on a lumped configuration but effectively includes the distributed properties of interconnect capacitance and resistance. CMOS device nonlinearity is simply approximated as a linear device. That is, the CMOS gate is modeled as a resistance at the driving port and a capacitance at a driven port. Interconnects are modeled as effective resistances and capacitances to match the distributed transmission behavior. The new model shows excellent agreement with SPICE simulations. Further, while existing models do not support the multiple line crosstalk behaviors, our model can be generalized to multiple lines. That is, unlike previously published work, even if the geometrical structures are not identical, it can accurately predict crosstalk. The model is experimentally verified with 0.35-μm CMOS process-based interconnect test structures. The new model can be readily implemented in CAD analysis tools. This model can be used to predict the signal integrity for high-speed and high-density VLSI circuit design     

Watt-level Ka- and Q-band MMIC power amplifiers operating at lowvoltages

Ka- and Q-band watt-level monolithic power amplifiers (PAs) operating at a low drain bias of 3.6 V are presented in this paper. Design considerations for low-voltage operation have been carefully studied, with an emphasis on the effect of device models. The deficiency of conventional table-based models for low-voltage operation is identified. A new nonlinear device model, which combines the advantages of conventional analytical models and table-based models, has been developed to circumvent the numerical problems and, thus, to predict optimum load impedance accurately. The model was verified with load-pull measurements at 39 GHz. To implement a low-voltage 1-W monolithic-microwave integrated-circuit amplifier, careful circuit design has been performed using this model. A Q-band two-stage amplifier showed 1-W output power with a high power gain of 15 dB at 3.6-V drain bias. The peak power-added efficiency (PAE) was 28.5% and 1-dB compression power (P_{1 dB}) was 29.7 dBm. A Ka-band two-stage amplifier showed a P_{1 dB} of 30 dBm with 24.5-dB associated gain and 32.5% PAE. Under very low dc power conditions (P_dc<2 W, V_ds=3.4 V), the amplifiers showed 29-dBm output power and PAE close to 36%, demonstrating ultimate low-power operation capability. To the best of our knowledge, this is the first demonstration of watt-level PA's under 3.6-V operation at 26 and 40 GHz. Compared with the published data, this work also represents state-of-the-art performance in terms of power gain, efficiency, and chip size     

Characterizing Overlay Multicast Networks and Their Costs

Overlay networks among cooperating hosts have recently emerged as a viable solution to several challenging problems, including multicasting, routing, content distribution, and peer-to-peer services. Application-level overlays, however, incur a performance penalty over router-level solutions. This paper quantifies and explains this performance penalty for overlay multicast trees via: 1) Internet experimental data; 2) simulations; and 3) theoretical models. We compare a number of overlay multicast protocols with respect to overlay tree structure, and underlying network characteristics. Experimental data and simulations illustrate that the mean number of hops and mean per-hop delay between parent and child hosts in overlay trees generally decrease as the level of the host in the overlay tree increases. Overlay multicast routing strategies, overlay host distribution, and Internet topology characteristics are identified as three primary causes of the observed phenomenon. We show that this phenomenon yields overlay tree cost savings: Our results reveal that the normalized cost L(n)/U(n) is propn^0.9 for small n, where L(n) is the total number of hops in all overlay links, U(n) is the average number of hops on the source to receiver unicast paths, and n is the number of members in the overlay multicast session. This can be compared to an IP multicast cost proportional to n^0.6 to n^0.8