Electron transport in InGaO3(ZnO)m (m=integer) studied using single-crystalline thin films and transparent MISFETs

We have investigated the characteristics of transparent metal-insulator-semiconductor field-effect transistors (MISFETs) fabricated using InGaO₃(ZnO)_m (m=integer) single-crystalline thin films as n-channel layers and amorphous alumina as gate insulator films. The MISFETs exhibit good characteristics such as insensitivity to visible light illumination, off-current as low as ∼1 nA with a positive threshold voltage of ∼3 V and on/off current ratio of 10⁵. The field-effect mobility increased from ∼1 to ∼10 cm² (V s)⁻¹ as the m-value increased. Room temperature Hall mobility also increased. However, unexpectedly these values were lower than the field-effect mobility. It is explained by existence of shallow localized state in the homologous compounds.     

Advanced process device technology for 0.3-μm high-performancebipolar LSIs

A new method is developed for forming shallow emitter/bases, collectors, and graft bases suitable for high-performance 0.3-μm bipolar LSIs. Fabricated 0.5-μm U-SICOS (U-groove isolated sidewall base contact structure) transistors are 44 μm², and they have an isolation width of 2.0 μm, a minimum emitter width of 0.2 μm, a maximum cutoff frequency (f_T) of 50 GHz, and a minimum ECL gate delay time of 27 ps. The key points for fabricating high-performance 0.3-μm bipolar LSIs are the control of the graft base depth and the control of the interfacial layer between emitter poly-Si and single-Si. The importance of a tradeoff relation between f_T and base resistance is also discussed     

A 6-ns ECL 100 K I/O and 8-ns 3.3-V TTL I/O 4-Mb BiCMOS SRAM

The authors report a 4 M word×1 b/1 M word×4 b BiCMOS SRAM that can be metal mask programmed as either a 6-ns access time for an ECL 100 K I/O interface to an 8-ns access time for a 3.3-V TTL I/O interface. Die size is 18.87 mm×8.77 mm. Memory cell size is 5.8 μm×3.2 μm. In order to achieve such high-speed address access times the following technologies were developed: (1) a BiCMOS level converter that directly connects the ECL signal level to the CMOS level; (2) a high-speed BiCMOS circuit with low threshold voltage nMOSFETs; (3) a design method for determining the optimum number of decoder gate stages and the optimum size of gate transistors; (4) high-speed bipolar sensing circuits used at 3.3-V supply voltage; and (5) 0.55-μm BiCMOS process technology with a triple-well structure     

A spot-size transformer based on mode interference

A novel mode-size transformer based on interference between guided and leaky modes is proposed and analyzed. Simulation shows significant improvement in spot-size transform efficiency per unit length, in comparison with the conventional tapered waveguide mode size converters based on mode evolution. Owing to its structural simplicity, easy fabrication is another merit of the new spot-size transformer     

Structure of microporous polypropylene sheets containing CaCO3 filler

The microporous polypropylene sheets were prepared by biaxially stretching polypropylene sheets containing CaCO₃ filler (particle size, 0.08–3.0 μm), when the CaCO₃ filler content was 59% by weight and the stretching ratio was 2.8 × 1.8. The microstructure of the sheets were investigated in relation to the CaCO₃ particle size by a N₂ gas permeation method. (1) Effective porosity increases with decreasing mean particle size of filler. (2) The tortuosity factor of the pore is in the range of 25–40 and becomes relatively smaller with decreasing mean particle size of filler. (3) The equivalent pore size becomes relatively smaller with decreasing mean particle size of filler.     

A novel on-chip electrostatic discharge (ESD) protection withcommon discharge line for high-speed CMOS LSIs

A novel on-chip electrostatic discharge (ESD) protection for high-speed CMOS LSI's that operate at higher than 500 MHz has been developed. Introduction of a newly developed common discharge line (CDL) can completely eliminate the protection device influence on the inner circuit operation. This enables minimization of the I/O capacitance by shrinking the dimension of the output transistor, which also serves as a protection device in conventional devices. This new protection (CDL protection) was applied to a high-speed DRAM of which I/O pin capacitance specification is 2 pF. As a result, the ESD tolerance of 4 kV for the charged device model test, 4 kV for the human body model test, and 700 V for the machine model test were obtained. In addition, the DRAM data rate higher than 660 MHz at room temperature was achieved. The results show significant improvement for both ESD and the I/O capacitance, compared with the conventional structure     

Phenotypic diversity and kinetics of proliferating microglia and astrocytes following cortical stab wounds

Brain injury induces reactive gliosis, characterized by increased expression of glial fibrillary acidic protein (GFAP), astrocyte hypertrophy, and hyperplasia of astrocytes and microglia. One hypothesis tested in this study was whether ganglioside GD3+ glial precursor cells would contribute to macroglial proliferation following injury. Adult rats received a cortical stab wound. Proliferating cells were identified by immunostaining for proliferating cell nuclear antigen (PCNA) and by [3H]-thymidine autoradiography, and cell phenotypes by immunocytochemical staining for GD3, GFAP, ED1 (for reactive microglia) and for Bandeiraea Simplicifolia isolectin-B4 binding (all microglia). Animals were labeled with thymidine at 1,2,3, and 4 days postlesion (dpl) and sacrificed at various times thereafter. Proliferating cells of each phenotype were quantified. A dramatic upregulation of GD3 on ramified microglia was seen in the ipsilateral hemisphere by 2 dpl. Proliferating cells consisted of microglia and fewer astrocytes. Microglia proliferated maximally at 2-3 dpl and one third to one half were GD3+. Astrocytes proliferated maximally at 3-4 dpl, and some were also GD3+. Both ramified and ameboid forms of microglia proliferated and by 4 dpl all GD3+ microglia were ED1+ and vice versa. In the contralateral cortex microglia expressed neither GD3 nor ED1. Thus they acquired these antigens when activated. Neither microglia nor astrocytes that were thymidine-labeled at 2, 3, or 4 dpl changed in number in subsequent days. Most thymidine+ astrocytes were large GFAP+ reactive cells that clearly arose from pre-existing astrocytes, not from GD3+ glial precursors. In this model of injury microglia proliferate earlier and to a much greater extent than astrocytes, they can divide when in ramified form, and GD3 is up-regulated in most reactive microglia and in a subset of reactive astrocytes. We also conclude that microglial proliferation precedes proliferation of invading blood-borne macrophages.     

Nondestructive readout mode static induction transistor (SIT) photosensors

The nondestructive readout (NDRO) performance of two static induction transistor (SIT) photosensors, a 40×40 pixel area array and a 140-b linear array, is examined. NDRO operation in the SIT sensors is demonstrated by imaging with the area array and by examining the output waveform of the linear array. The charge lost per NDRO cycle in the linear array was 0.014% near the saturation signal level, and no charge loss could be detected at the ⩽0.5 saturation level. NDRO performance in the area array was degraded compared to the linear array, due to the larger value of the load capacitance connected to the output electrode of the SIT. NDRO operation also enables the cancellation of both the photosite reset noise and the signal nonuniformity by subtracting the first NDRO output from the following NDRO outputs, as well as the advantage of monitoring the signal state during the integration period