Design Methodology for Throughput Optimum Architectures of Hash Algorithms of the MD4-class

In this paper we propose an architecture design methodology to optimize the throughput of MD4-based hash algorithms. The proposed methodology includes an iteration bound analysis of hash algorithms, which is the theoretical delay limit, and Data Flow Graph transformations to achieve the iteration bound. We applied the methodology to some MD4-based hash algorithms such as SHA1, MD5 and RIPEMD-160. Since SHA1 is the algorithm which requires all the techniques we show, we also synthesized the transformed SHA1 algorithm in a 0.18 μm CMOS technology in order to verify its correctness and its achievement of high throughput. To the best of our knowledge, the proposed SHA1 architecture is the first to achieve the theoretical throughput optimum beating all previously published results. Though we demonstrate a limited number of examples, this design methodology can be applied to any other MD4-based hash algorithm.     

High-throughput programmable cryptocoprocessor

High-speed Internet protocol security (IPsec) applications require high throughput and flexible security engines. A loosely coupled cryptocoprocessor based on the advanced encryption standard combines high throughput with programmability. using domain-specific instructions and design principles such as control hierarchy and block pipelining, the security engine supports Internet protocol security and other networking applications.     

Design of an Interconnect Architecture and Signaling Technology for Parallelism in Communication

The need for efficient interconnect architectures beyond the conventional time-division multiplexing (TDM) protocol-based interconnects has been brought on by the continued increase of required communication bandwidth and concurrency of small-scale digital systems. To improve the overall system performance without increasing communication resources and complexity, this paper presents a cost-effective interconnect architecture, communication protocol, and signaling technology that exploits parallelism in board-level communication, resulting in shorter latency and higher concurrency on a shared bus or link: the proposed source synchronous CDMA interconnect (SSCDMA-I) enables dual concurrent transactions on a single wire line as well as flexible input/output (I/O) reconfiguration. The SSCDMA-I utilizes 2-bit orthogonal CDMA coding and a variation of source synchronous clocking for multilevel superposition; a single 3-level SSCDMA-I line operates as if it consists of dual virtual time-multiplexed interconnects, which exploits communication parallelism with a reduced number of pins, wires, and complexity. The unique multiple access capability of the SSCDMA-I improves real-time communication between multiple semiconductor intellectual property (IP) blocks on a shared link or bus by reducing the bus contention interference from simultaneous traffic requests and by taking advantage of shorter request latency. The prototype transceiver chip is implemented in 0.18-m CMOS and the 10-cm test PC board system achieves an aggregate data rate of 2.5 Gb/s/pin between four off-chip (2Tx-to-2Rx) I/Os.     

Domain Specific Tools and Methods for Application in Security Processor Design

Security processors are used to implement cryptographic algorithmswith high throughput and/or low energy consumption constraints. The designof these processors is a balancing act between flexibility and energy consumption.The target is to create a processor with just enough programmability to covera set of algorithms—an application domain. This paper proposes GEZEL,a design environment consisting of a design language and an implementationmethodology that can be used for such domain specific processors. We use thesecurity domain as driver, and discuss the impact of the domain on the targetarchitecture. We also present a methodology to create, refine and verify asecurity processor.     

Security and performance optimization of a new DES data encryptionchip

The implementation of a high-performance data encryption standard (DES) data encryption chip is presented. At the system design level, cryptographical optimizations and equivalence transformations lead to a very efficient floorplan with minimal routing, which otherwise would present a serious problem for data-scrambling algorithms. These optimizations, which do not compromise the DES algorithm nor the security, are combined with a highly structured design and layout strategy. Novel CAD tools are used at different steps in the design process. The result is a single chip of 25 mm² in 3-μm double-metal CMOS. Functionality tests show that a clock of 16.7 MHz can be applied, which means that a 32-Mb/s data rate can be achieved for all eight byte modes. This is the fastest DES chip reported yet, allowing equally fast execution of all four DES modes of operation, due to an original pipeline architecture     

In-place memory management of algebraic algorithms on application specific ICs

High level memory management is an important step during the automatic synthesis of application specific micro coded processors aimed at multi-dimensional signal processing in real-time. For given throughput and I/O flow requirements, the objective is to derive the optimal background memory organization where the cost due to storage size and address requirements are minimized. In this paper, a contribution will be proposed to this complex problem. A strategy will be presented to detect the possibility forin-place storage and to deduce thememory requirements for the implementation of numerical matrix type of algorithms on a single ASIC chip.