A monolithic three-channel LD-PD array with vertically staggeredfacets for autofocusing reflectivity sensors

A monolithic three-channel LD-PD array with vertically staggered facets is proposed for an autofocusing reflectivity sensor which uses light feedback. The focus-sensing characteristics are investigated using an array with a radiation facet displacement of 12 μm and an interchannel distance of 130 μm, fabricated on an 830-nm AlGaAs/GaAs multiple-quantum-well laser substrate with buried-heterostructure stripe geometry waveguides. High focus-sensing accuracy is achieved. A potential application of the array to optical heads for phase change media is discussed     

Advanced process device technology for 0.3-μm high-performancebipolar LSIs

A new method is developed for forming shallow emitter/bases, collectors, and graft bases suitable for high-performance 0.3-μm bipolar LSIs. Fabricated 0.5-μm U-SICOS (U-groove isolated sidewall base contact structure) transistors are 44 μm², and they have an isolation width of 2.0 μm, a minimum emitter width of 0.2 μm, a maximum cutoff frequency (f_T) of 50 GHz, and a minimum ECL gate delay time of 27 ps. The key points for fabricating high-performance 0.3-μm bipolar LSIs are the control of the graft base depth and the control of the interfacial layer between emitter poly-Si and single-Si. The importance of a tradeoff relation between f_T and base resistance is also discussed     

Amplified distributed reflective optical star couplers

A practical configuration for an amplified distributed reflective N-star coupler using 2×2 3-dB fiber couplers and minimum numbers of erbium-doped fibers, pump lasers, and standard fibers is presented. The constitution and characteristics of this coupler are investigated. Besides a tremendous amount of saving of the required standard fibers, this distributed coupler is more efficient, more reliable, more flexible for future expansion, and more cost-effective for application in optical networks     

Radar reflectivity in snowfall

Backscattering properties of dry snowflakes at different microwave frequencies are examined. It is shown that the Rayleigh approximation does not often provide the necessary accuracy for snowflake reflectivity calculations for radar wavelengths used in meteorology; however, another simple approximation, the Rayleigh-Gans approximation, can be safely used for such calculations. Reflectivity-snowfall rate relationships are derived for different snow densities and different radar frequencies. It is shown that dual-wavelength radar measurements can be used for estimating the effective sizes of snowflakes. Experimental data obtained during radar snowfall measurements in the WISP project of 1991 with the NOAA X- and Ka-band radars are found to be consistent with the described theoretical results     

The process window of a-Si/Ti bilayer metallization for anoxidation-resistant and self-aligned TiSi2 process

The dependences of both oxidation-resistant and self-aligned silicidation properties on the thicknesses of top amorphous-Si (a-Si) and Ti metal in an a-Si/Ti bilayer process are presented. It is shown that a thin silicide layer formed during the reaction between a-Si and Ti films becomes a stable oxidation and nitridation barrier for oxygen- and nitrogen-related impurities. Moreover, the formation sequence of the silicide phase depends not only on the annealing temperature but also on the thickness of the Ti film. In addition, the preferential orientation of the silicide phase after annealing at high temperature also shows a strong dependence on the thickness of Ti film, which is attributed to the difference of the grain size in the polycrystalline silicide film. The allowed process window for the a-Si thickness can be determined experimentally and a reproducible and homogeneous self-aligned TiSi₂ film can be easily obtained by using the a-Si/Ti bilayer process in salicide applications despite high-level contaminations of oxygen impurities in both the as-deposited Ti film and the annealing ambient     

A 14-ns 14-Mb CMOS DRAM with 300-mW active power

A 4-Mb high-speed DRAM (HSDRAM) has been developed and fabricated by using 0.7-μm L_eff CMOS technology with PMOS arrays inside n-type wells and p-type substrate plate trench cells. The 13.18-mm×6.38-mm chip, organized as either 512 K word×8 b or 1 M word×4 b, achieves a nominal random-access time of 14 ns and a nominal column-access time of 7 ns, with a 3.6-V V_cc and provision of address multiplexing. The high level of performance is achieved by using a short-signal-path architecture with center bonding pads and a pulsed sensing scheme with a limited bit-line swing. A fast word-line boosting scheme and a two-stage word-line delay monitor provide fast word-line transition and detection. A new data output circuit, which interfaces a 3.6-V V_cc to a 5-V bus with an NMOS-only driver, also contributes to the fast access speed by means of a preconditioning scheme and boosting scheme. Limiting the bit-line voltage swing for bit-line sensing results in a low power dissipation of 300 mW for a 60-ns cycle time     

Diode-HBT-logic circuits monolithically integrable with ECl/CMLcircuits

A novel logic approach, diode-HBT logic (DHL), that is implemented with GaAlAs/GaAs HBTs and Schottky diodes to provide high-density and low-power digital circuit operation is described. This logic family was realized with the same technology used to produce emitter-coupled-logic/current-mode-logic (ECL/CML) circuits. The logic operation was demonstrated with a 19-stage ring oscillator and a frequency divider. A gate delay of 160 ps was measured with 1.1 mW of power per gate. The divider worked properly up to 6 GHz. Layouts of a DHL flip-flop and divider showed that circuit area and transistor count can be reduced by about a factor of 3, relative to ECL/CML circuits. The new logic approach allows monolithic integration of high-speed ECL/CML circuits with high-density DHL circuits with high-density DHL circuits     

Historical review of OCR research and development

Research and development of OCR systems are considered from a historical point of view. The historical development of commercial systems is included. Both template matching and structure analysis approaches to R&D are considered. It is noted that the two approaches are coming closer and tending to merge. Commercial products are divided into three generations, for each of which some representative OCR systems are chosen and described in some detail. Some comments are made on recent techniques applied to OCR, such as expert systems and neural networks, and some open problems are indicated. The authors' views and hopes regarding future trends are presented     

Computer recognition of unconstrained handwritten numerals

Four independently, developed expert algorithms for recognizing unconstrained handwritten numerals are presented. All have high recognition rates. Different experimental approaches for incorporating these recognition methods into a more powerful system are also presented. The resulting multiple-expert system proves that the consensus of these methods tends to compensate for individual weaknesses, while preserving individual strengths. It is shown that it is possible to reduce the substitution rate to a desired level while maintaining a fairly high recognition rate in the classification of totally unconstrained handwritten ZIP code numerals. If reliability is of the utmost importance, substitutions can be avoided completely (reliability=100%) while retaining a recognition rate above 90%. Results are compared with those for some of the most effective numeral recognition systems found in the literature     

Deep-submicrometer large-angle-tilt implanted drain (LATID)technology

Deep-submicrometer large-angle-tilt implanted drain (LATID) technology is described. It is found by Monte Carlo process simulation and SIMS measurements that a sufficiently long n^- region can be formed under the gate by taking advantage of large-angle-tilt implant and successfully without ion channeling by taking care of the implant direction. A design that offsets the n⁺ implant by sidewall spacers to suppress the n⁺-gate overlap to zero while keeping the n^- region fully overlapped with the gate is found to be crucial for improved performance and reliability. The device performance, such as current drivability and short-channel effects, is described, and the circuit speed is investigated. Hot-carrier effects such as lateral electric field and device lifetime over a wide range of drain structures are also investigated. The tradeoff between device performance and hot-carrier reliability in deep-submicrometer LATID FETs is discussed