A 320 MFLOPS CMOS floating-point processing unit for superscalarprocessors

A CMOS pipelined floating-point processing unit (FPU) for superscalar processors is described. It is fabricated using a 0.5 μm CMOS triple-metal-layer technology on a 61 mm² die. The FPU has two execution modes to meet precise scientific computations and real-time applications. It can start two FPU operations in each cycle, and this achieves a peak performance of 160 MFLOPS double or single precision with an 80 MHz clock. Furthermore, the original computation mode, twin single-precision computation, double the peak performance and delivers 320 MFLOPS single precision. Its full bypass reduces the latency of operations, including load and store, and achieves an effective throughput even in nonvectorizable computations. An out-of-order completion is provided by using a new exception prediction method and a pipeline stall technique     

Study of BiCMOS logic gate configurations for improved low-voltageperformance

A simple BiCMOS configuration employing the source-well tie PMOS/n-p-n pull-down combination is proposed for low-voltage, high-performance operations. The improved BiCMOS gate delay time over that of the NMOS/n-p-n (conventional) BiCMOS gate is confirmed by means of inverter simulations and measured ring oscillator data. The source-well tie PMOS/n-p-n BiCMOS gate outperforms its conventional BiCMOS counterpart in the low-voltage supply range, at both high and low temperatures. A critical speed path from the 68030 internal circuit is used as a benchmark for the proposed BiCMOS design technique. The measured propagation delay of the BiCMOS speed path is faster than its CMOS counterpart down to 2.3 V supply voltage at -10°C and sub-2 V at 110°C     

The process dependence on positive bias temperature aginginstability of p+(B) polysilicon-gate MOS devices

During positive bias temperature (BT) aging, a large number of interface traps on p⁺(B) polysilicon MOS devices are generated in the upper half of the bandgap without an increase in the charges trapped in the gate oxide. The increase in interface traps can be reduced by processes which exclude the hydrogen included during fabrication. The increase in the interface-state density is explained as follows. The generation of the interface traps is caused by hydrogen ions reaching at the SiO₂/Si interface through the gate oxide from the polysilicon-gate electrode. The hydrogen ions combine with activated boron and are released from the boron under positive BT aging. The increase in interface traps is formulated by equations which are derived from the above model     

Experimental demonstration of soliton data transmission over unlimited distances with soliton control in time and frequency domains

A 2/sup 9/-1 pseudorandom-binary-sequence soliton signal has been transmitted experimentally over one million km for the first time with no degradation in the bit error rates. The synchronous modulator was driven by a timing clock signal extracted from the transmitting data signal. These results mean that it is possible to send soliton data signals over unlimited distances through the use of soliton control in the time and frequency domains.<>     

R-MOSFET structure based on current division

A parallel-path combination of resistors and MOSFETs is proposed for use in integrated continuous-time filters and other circuits. The technique allows continuous incremental tuning while maintaining significantly better linearity than MOSFET-only structures.<>     

Highly efficient and tunable Nd/sup 3+/ doped fluoride fibre laser operating in 1-3 mu m band

A highly efficient and tunable Nd/sup 3+/ doped fluoride fibre laser operating in the 1.3 mu m band pumped at 0.8 mu m is demonstrated. The pump laser is a titanium sapphire laser and the tuning element is a dielectric multicoated bandpass filter inserted in the cavity. The oscillation wavelength was successfully tuned from 1.315 to 1.348 mu m for the first time.<>     

Scale and rotation invariant pattern recognition using complex-log mapping and augmented second order neural network

A scale and rotation invariant pattern recognition system using complex-log mapping (CLM) and an augmented second order neural network (SONN) is proposed. CLM is very useful for extracting the scale and rotation invariant features. The results are, however, given in a wrap-around translated form. This problem is solved with an augmented SONN. Experimental results show that the proposed system has improved recognition performance.<>     

MetaRing-a full-duplex ring with fairness and spatial reuse

The design principles of a ring network with spatial bandwidth reuse are described. A distributed fairness mechanism for this architecture, which uses low latency hardware control signals, is presented. The basic fairness mechanism can be extended for implementing multiple priority levels and integration of asynchronous with synchronous traffic. The ring is full-duplex and has two basic modes of operation: buffer insertion mode for variable-size packets and slotted mode for fixed-size packets or cells. Concurrent access and spatial reuse allow simultaneous transmissions over disjoint segments of a bidirectional ring and can increase the effective throughput by a factor of four or more. The combination of a full-duplex ring, spatial reuse, a reliable fairness mechanism, and the exploitation of advent in fiber-optic technology are the basis for the MetaRing network architecture     

On self-routing in Clos connection networks

A self-routing connection network is a switching device where the routing of each switch can be determined in terms of the destination addresses of its inputs alone, i.e. independent of the routing information regarding the other switches in the network. One family of connection networks that were considered in the literature for self-routing are Clos networks. Earlier studies indicate that some Clos networks can be self-routed for certain permutations. In this paper, it is proved that the only category of Clos networks that can be self-routed for all permutations are those with at most two switches in their outer stages     

RATAN-600: the World's biggest reflector at the `cross roads'

The RATAN-600 new-technology telescope, which supplies about one-quarter of the observational material in Russia in the field of radio astronomy and more than 80% in the central, centimeter-decimeter range, is described. The RATAN-600 is the first multi-element-reflector radio telescope without any structure linking the surface elements. The functions normally performed by such structure are executed by the Earth's surface. It is also the first radio telescope with a controlled-shape surface. In observations at different elevations above the horizon, the shape of its surface varies, remaining in the family of second-order surfaces. The RATAN-600 is also the first aperture-synthesis reflector-type telescope. The location of the radio telescope, its design, its modes of operation, and its future prospects are discussed