Practical OSPF traffic engineering

Open Shortest Path First (OSPF) traffic engineering (TE) is intended to bring long-awaited traffic management capabilities into IP networks, which still rely on today's prevailing routing protocols: OSPF or IS-IS. In OSPF, traffic is forwarded along, and split equally between, equal cost shortest paths. In this letter, we formulate the basic requirements placed on a practical TE architecture built on top of OSPF and present a theoretical framework meeting these requirements of practicality. The main contribution of our work comes from the recognition that coupled with an instance of the maximum throughput problem there exists a related inverse shortest-path problem yielding optimal OSPF link weights.     

Finite element analysis of advanced multilayer capacitors

We establish a systematic methodology to design and analyse electromagnetic components such as advanced multilayer ceramic capacitors (MLCCs) using the finite element (FE) method. We employ a coupled formulation to compute the interaction between the electric and magnetic fields. Unlike a linear distribution of current assumed in the circuit model, an accurate electrostatic solution to model the entire advanced MLCCs (4 × 4 × 27 = 432 cells) is presented. The FE solution is used to compute the lumped parameters for a range of frequencies. These lumped parameters are then used to compute the parasitic elements of the MLCCs. We introduce two algorithms to efficiently analyse the behaviour of a capacitor with changing frequency. The lower frequency (much below the self‐resonant frequency of the capacitor) algorithm separates the effect of the electric and magnetic fields and reduces the computational effort required to solve the FE problem, whereas, the high‐frequency algorithm couples the effect between the electric and the magnetic fields. We use these algorithms in conjunction with a new multiple scale technique to effectively determine the small values of R, L and C in MLCCs. The formulation, the implementation, and the numerical results demonstrate the efficacy of the present FE formulation and establish a systematic methodology to design and analyse advanced electromagnetic components. Copyright © 2003 John Wiley & Sons, Ltd.     

Asymptotic performance of single parity-check product codes

This article investigates the asymptotic performance of single parity-check (SPC) product codes (PCs) from a decoding point of view. Specifically, the probability of bit error is bounded before and after the decoding of each dimension, similar to the analysis of "iterated codes" by Elias (1954). It is shown that the asymptotic probability of bit error can be driven to zero as the number of dimensions, and hence the block length, increases at signal-to-noise ratios (SNRs) within 2 dB of capacity over the additive white Gaussian noise (AWGN) channel.     

Exposed Die-Top Encapsulation Molding for an Improved High- Performance Flip Chip BGA Package

The recent advancement in high- performance semiconductor packages has been driven by the need for higher pin count and superior heat dissipation. A one-piece cavity lid flip chip ball grid array (BGA) package with high pin count and targeted reliability has emerged as a popular choice. The flip chip technology can accommodate an I/O count of more than five hundreds500, and the die junction temperature can be reduced to a minimum level by a metal heat spreader attachment. None the less, greater expectations on these high-performance packages arose such as better substrate real estate utilization for multiple chips, ease in handling for thinner core substrates, and improved board- level solder joint reliability. A new design of the flip chip BGA package has been looked into for meeting such requirements. By encapsulating the flip chip with molding compound leaving the die top exposed, a planar top surface can be formed. A, and a flat lid can then be mounted on the planar mold/die top surface. In this manner the direct interaction of the metal lid with the substrate can be removed. The new package is thus less rigid under thermal loading and solder joint reliability enhancement is expected. This paper discusses the process development of the new package and its advantages for improved solder joint fatigue life, and being a multichip package and thin core substrate options. Finite-element simulations have been employed for the study of its structural integrity, thermal, and electrical performances. Detailed package and board-level reliability test results will also be reported     

On the effect of spatial variances in historical rainfall time series to CSO performance evaluation.

Historical, high-resolution rain series are the backbone of modern combined sewer overflow (CSO) structure design. These rain series are the input to the computational estimation of the performance of the measures with respect to CSO pollution abatement. However, those historical precipitation measurements are available at only a few locations. Frequently rain series have to be used from gauging stations at a significant distance. In order to judge and to compensate for this influence an estimate between rain characteristics and combined sewer outflow (CSO) performance indicators would be useful. In this paper such correlations have been sought for a collection of 37 rain series covering large areas of Europe. It was found that the mean annual rain volume can explain most of the variances for the performance indicators Number of overflows and CSO volume. For explaining the spatial differences in the efficiency of the CSO structure another rain characteristic, i.e. the maximum event with a return period of one year, is to be used.     

TEM Studies of High Temperature Corrosion Behaviour of TiAl Intermetallics with Surface Modifications

The oxidation/sulphidation behaviour of a Ti‐46.7Al‐1.9W‐0.5Si alloy with a TiAl₃ diffusion coating was studied in an environment of H₂/H₂S/H₂O at 850^oC. The kinetic results demonstrate that the TiAl₃ coating significantly increased the high temperature corrosion resistance of Ti‐46.7Al‐1.9W‐0.5Si. The SEM, EDX, XRD and TEM analysis reveals that the formation of an Al₂O₃ scale on the surface of the TiAl₃‐coated sample was responsible for the enhancement of the corroison resistance. The Ti‐46.7Al‐1.9W‐0.5Si alloy was also modified by Nb ion implantation. The Nb ion implanted and as received sampels were subjected to cyclic oxidation in an open air at 800^oC. The Nb ion implantation not only increased the oxidation resistance but also substantially improved the adhesion of scale to the substrate.     

Reliability studies of MOCVD TiSiN and EnCoRe Ta(N)/Ta

Passivated single damascene copper SiO₂ damascene lines were evaluated in combination with TiSiN and Ta(N)/Ta diffusion barriers. Leakage current, breakdown and time-dependent dielectric breakdown properties were investigated on a wafer level basis for temperatures ranging between room temperature and 150 °C. It is found that the leakage performance of the wafers with a TiSiN barrier is better at room temperature, but at 150 °C the performance levels out with Ta(N)/Ta. Time-dependent dielectric breakdown measurements at 150 °C show that the lifetime of the interconnect is higher with the selected Ta(N)/Ta barrier than for TiSiN.