Novel GaAs enhancement-mode/depletion-mode pHEMTs technology using high-k praseodymium oxide interlayer

In this study, a novel metal–semiconductor gate enhancement-mode (E-mode) and a metal–insulator-metal–semiconductor (MIMS) gate depletion-mode (D-mode) AlGaAs/InGaAs pseudomorphic high electron mobility transistor (pHEMT) on a single GaAs substrate have been developed by using high dielectric constant praseodymium insulator layer. The epitaxial layers were design for an enhancement-mode pHEMT after gate recess process. To achieve E/D-mode pHEMTs on single GaAs wafer, traditional Pt/Ti/Au metals were deposited as Schottky contact for E-mode pHEMTs and Pr/Pr₂O₃/Ti/Au were deposited as MIMS-gate for D-mode pHEMTs. This AlGaAs/InGaAs E-mode pHEMTs exhibit a gate turn-on voltage (V_ON) of +1 V and a gate-to-drain breakdown voltage of ?5.6 V, and these values were +7 V and ?34 V for MIMS-gate D-mode pHEMTs, respectively. Therefore, this high-k insulator in D-mode pHEMT is beneficial for suppressing the gate leakage current. Comparing to previous E/D-mode pHEMT technology, this E-mode pHEMTs and MIMS-gate D-mode pHEMTs exhibit a highly potential for high uniformity GaAs logic circuit applications due to its single recess process.     

Fault-Tolerant Mesh-Based NoC with Router-Level Redundancy

The aggressively scaled CMOS technology is increasingly threatening the dependability of network-on-chips (NoCs) architecture. In a mesh-based NoC, a faulty router or broken link may isolate a well functional processing element (PE). Also, a set of faulty routers may form isolated regions, which can degrade the design. In this paper, we propose a router-level redundancy (RLR) fault-tolerant scheme that differs from the traditional microarchitecture-level redundancy (MLR) approach to relieve the problem of isolated PE and isolated region. By simply adding one spare router within each router set in a mesh, RLR can be created and connection paths between adjacent routers can be diversified. To exploit this extra resource, two reconfiguration algorithms are demonstrated to detour observed faulty routers/links. The proposed RLR fault-tolerant scheme can tolerate at most one faulty router within a router set. After the reconfiguration, the original mesh topology is maintained. As a result, the proposed architecture does not need any support from the network layer routing algorithms. The scheme has been evaluated based on the three fault-tolerant metrics: reliability, mean time to failure (MTTF), and yield. The experimental results show that the performance RLR increases as the size of NoC grows; however, the relative connection cost decreases at the same time. This characteristic makes our architecture suitable for large-scale NoC designs.

     

Comparison of self‐adaptive dynamic differential evolution and particle swarm optimization for smart antennas in wireless communication

In this paper, ultrawide band (UWB) communication systems with eight transmitting and receiving ring antenna arrays are implemented to test the bit error rate and capacity performance. By using the ray‐tracing technique to compute any given indoor wireless environment, the impulse response of the system can be calculated. The synthesized beamforming problem can be reformulated into a multiobjective optimization problem. Self‐adaptive dynamic differential evolution (SADDE) and particle swarm optimization (PSO) are used to find the excitation current and the feed line length of each antenna to form the appropriate beam pattern. This pattern can then reduce the bit error rate and increase the channel capacity and receiving energy. Numerical results show that the fitness value and the convergence speed by the SADDE are better than those by the PSO. Moreover, the SADDE had better results for both line‐of‐sight and nonline‐of‐sight cases. In other words, compared with PSO, SADDE has improved more effectively the main beam radiation energy and reduced the multipath interference.     

InGaP/InGaAs Pseudomorphic Heterodoped-Channel FETs With a Field Plate and a Reduced Gate Length by Splitting Gate Metal

Depositing gate metal across a step undercut between the Schottky barrier layer and the insulator-like layer is employed to obtain a reduced gate length of 0.4 mum with an additional 0.6-mum field plate from a 1-mum gate window. Most dc and ac characteristics including current density (I_DSS=451mA/mm), transconductance (g_m,max=225mS/mm), breakdown voltages (V_BD(DS)/V _BD(GD)=22/-25.5V), gate-voltage swing (GVS=2.24V), cutoff, and maximum oscillation frequencies (f_t/f_max=17.2/32GHz) are improved as compared to those of a 1-mum gate device without field plate. At a V_DS of 4.0 V, a maximum power added efficiency of 36% with an output power of 13.9 dBm and a power gain of 8.7 dB are obtained at a frequency of 1.8 GHz. The saturated output power and the linear power gain are 316 mW/mm and 13 dB, respectively     

Inverse scattering of inhomogeneous biaxial materials coated on aconductor

The inverse scattering of inhomogeneous biaxial materials coated on a perfectly conducting cylinder with known cross section is investigated. A group of unrelated incident waves is used to illuminate the cylinder. By properly arranging the direction and polarization of various unrelated incident waves, the difficulties of ill-posedness and nonlinearity were circumvented and the permittivity tensor distribution can be reconstructed through simple matrix operations. For theoretical formulation based on the boundary condition, a set of integral equations is derived and solved by the moment method as well as the unrelated illumination method. Numerical results show that the permittivity tensor distribution of the materials can be successfully reconstructed even when the permittivity is fairly large. Good reconstruction has been obtained both with and without Gaussian noise in measured data. In addition, the effect of noise contamination on imaging is also examined     

A novel complementary Colpitts differential CMOS VCO with low phase noise performance

A low phase noise Ka-band CMOS voltage-controlled oscillator is proposed in this paper. A new complementary Colpitts structure was adopted in a 0.18-μm CMOS process to achieve differential-ended outputs, low phase-noise performance, and low-power consumption. The designed VCO oscillates from 29.8 to 30 GHz with 200 MHz tuning range. The measured phase noise at 1-MHz offset is −109 dBc/Hz at 30 GHz and −105.5 dBc/Hz at 29.8 GHz. The power consumption of VCO is only 27 mW. In addition, compared with the published papers, the proposed CMOS VCO achieves the best figure of merit (FOM) of −185 dB at 29.95-GHz band.     

Self-Assembled Two-Dimensional Surface Structures for Beam Shaping of GaN-Based Vertical-Injection Light-Emitting Diodes

Enhanced light extraction and beam shaping of GaN-based vertical-injection light-emitting diodes (VI-LEDs) employing biomimetic surface structures were demonstrated. The biomimetic surface structures were fabricated using self-assembled polystyrene nanospheres serving as a monolayer mask, and followed by anisotropic inductively coupled plasma reactive ion etching. The light output power of the VI-LEDs with the patterned structures exhibited an efficiency enhancement factor of 68% at a driving current of 350 mA, compared to those without any surface structures. The structures also resulted in a modified heart-shaped radiation pattern, which is preferable for backlight applications in flat panel displays.     

Helical‐Like 3D Ultrathin Piezoelectric Element for Complicated Ultrasonic Field

The developments of personalized medicine, ultrasound imaging, and contactless “microscopic handle” techniques are pushing ultrasonic transducers toward features of high frequency, device miniaturization, and even novel function. However, the conventional ultrasonic transducer has severely limited the development of novel ideas for applications due to its ordinary ultrasonic field. Although transducer arrays and monolithic acoustic holograms are capable of producing the complicated ultrasonic field, it is still difficult to achieve high frequency, device miniaturization, and novel function simultaneously. Here, a simple but effective approach is introduced that aims at reconstructing the complicated and high‐frequency ultrasonic field via a compact single‐element ultrasonic transducer. The 3D ultrathin piezoelectric element with a complex configuration is demonstrated theoretically and experimentally to produce the desired complicated ultrasonic field. With helical‐like configuration, the single‐element ultrasonic transducer offers efficient noncontact trapping and manipulation of suspended microparticles and biological cells. Moreover, its strong trapping capability leads to the 3D stacking of microparticles, which is a novel and interesting phenomenon achieved by a single‐element ultrasonic transducer. This work brings the possibility of a complicated ultrasonic field for achieving novel high‐frequency ultrasound applications through the design of smart structure ultrathin piezoelectric materials.     

A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM

In this paper we propose a novel built-in self-test (BIST) design for embedded SRAM cores. Our contribution includes a compact and efficient BIST circuit with diagnosis support and an automatic diagnostic system. The diagnosis module of our BIST circuit can capture the error syndromes as well as fault locations for the purposes of repair and fault/failure analysis. In addition, our design provides programmability for custom March algorithms with lower hardware cost. The combination of the on-line programming mode and diagnostic system dramatically reduces the effort in design debugging and yield enhancement. We have designed and implemented test chips with our BIST design. Experimental results show that the area overhead of the proposed BIST design is only 2.4% for a 128 KB SRAM, and 0.65% for a 2 MB one.