Colloidal templating for producing hollow ZnO shells: Fabrication, growth and electrical properties

Colloidal templating and pulsed laser deposition (PLD) have been combined to fabricate arrays of ordered two-dimensional hollow ZnO shells. Templates were formed by spin-coating colloidal solutions containing monodispersed polymethylmethacrylate (PMMA) beads. The optimum condition for forming templates of ordered two-dimensional geometry was deduced by calculating the radial distribution functions. On templates ZnO films were deposited by a PLD method. Upon annealing ZnO films crystallize into a würtzite structure. The surface morphology of hollow ZnO shells consists of protruding columnar nano-crystallites with no distinct ZnO texture. The electrical properties were measured as a function of annealing temperature. The electrical conductivity increases with increase in annealing temperature. The activation energy was estimated to be 0.7 eV. The change in the electrical properties upon grain growth has been attributed to alteration in the fraction site availability for defect formation at the grain boundaries.     

Green electroluminescent diode from poly(2-trimethylsilyl-1,4-phenylene vinylene)

Summary Poly(2-trimethylsilyl-1,4-phenylenevinylene) (TMS-PPV) was synthesized through a organic-soluble precursor polymer, and its properties were characterized by UV-visible, FT-IR spectroscopy and thermal anaylsis. The EL devices were fabricated with TMS-PPV as an emitting layer, and ITO and aluminum as positive and negative electrodes, respectively. Threshold voltage of the device was about 15 V and the emission maximum was at about 540 nm with quantum efficiency of 3.5x10^-4% photons per electron in air and room temperature condition.     

Low Temperature Characteristics of Schottky Barrier Single Electron and Single Hole Transistors

Schottky barrier single electron transistors (SB‐SETs) and Schottky barrier single hole transistors (SB‐SHTs) are fabricated on a 20‐nm thin silicon‐on‐insulator substrate incorporating e‐beam lithography and a conventional CMOS process technique. Erbium‐ and platinum‐silicide are used as the source and drain material for the SB‐SET and SB‐SHT, respectively. The manufactured SB‐SET and SB‐SHT show typical transistor behavior at room temperature with a high drive current of 550 μA/μm and ?376 μA/μm, respectively. At 7 K, these devices show SET and SHT characteristics. For the SB‐SHT case, the oscillation period is 0.22 V, and the estimated quantum dot size is 16.8 nm. The transconductance is 0.05 μS and 1.2 μS for the SB‐SET and SB‐SHT, respectively. In the SB‐SET and SB‐SHT, a high transconductance can be easily achieved as the silicided electrode eliminates a parasitic resistance. Moreover, the SB‐SET and SB‐SHT can be operated as a conventional field‐effect transistor (FET) and SET/SHT depending on the bias conditions, which is very promising for SET/FET hybrid applications. This work is the first report on the successful operations of SET/SHT in Schottky barrier devices.