The Piracicaba river basin is a subtropical watershed located in the southeastern region of Brazil. With an area of 12 400 km2, the basin is a typical example of new landscape resulting from development in tropical and sub-tropical regions: establishment of intensive industrial and agricultural processes were followed by significant population growth and water management. This scenario has led to significant increase in water demand and decrease in water quality. The main objective of this study is the detection of changes in the patterns of flow and precipitation in the basin, and its possible relation to man-induced changes. Statistical analyses were performed on records of precipitation, evapotranspiration and streamflow, from 1947 to 1991. Precipitation and evapotranspiration totals showed significant increasing trends for the entire basin. From eight streamflow gauge stations, half showed significant decreasing trend. The most probable cause of such trends is the export of water from the basin to the metropolitan region of São Paulo city. 相似文献
The versatility of a fluoro‐containing low band‐gap polymer, poly[2,6‐(4,4‐bis(2‐ethylhexyl)‐4H‐cyclopenta[2,1‐b;3,4‐b’]dithiophene)‐alt‐4,7‐(5‐fluoro‐2,1,3‐benzothia‐diazole)] (PCPDTFBT) in organic photovoltaics (OPVs) applications is demonstrated. High boiling point 1,3,5‐trichlorobenzene (TCB) is used as a solvent to manipulate PCPDTFBT:[6,6]‐phenyl‐C71‐butyric acid methyl ester (PC71BM) active layer morphology to obtain high‐performance single‐junction devices. It promotes the crystallization of PCPDTFBT polymer, thus improving the charge‐transport properties of the active layer. By combining the morphological manipulation with interfacial optimization and device engineering, the single‐junction device exhibits both good air stability and high power‐conversion efficiency (PCE, of 6.6%). This represents one of the highest PCE values for cyclopenta[2,1‐b;3,4‐b’]dithiophene (CPDT)‐based OPVs. This polymer is also utilized for constructing semitransparent solar cells and double‐junction tandem solar cells to demonstrate high PCEs of 5.0% and 8.2%, respectively. 相似文献
This paper proposes a new approach to measure the distortion introduced by changing individual edge pixels in binary text images. The approach considers not only how many pixels are changed but also where the pixels are changed and how the flipping affects the overall shape formed by the edge line. Similarities between the edge line segments in the original and distorted image are compared to measure the distortion. Subjective testing shows that the new distortion measure correlates well with human visual perception. 相似文献
N‐type doping of GaAs nanowires has proven to be difficult because the amphoteric character of silicon impurities is enhanced by the nanowire growth mechanism and growth conditions. The controllable growth of n‐type GaAs nanowires with carrier density as high as 1020 electron cm?3 by self‐assisted molecular beam epitaxy using Te donors is demonstrated here. Carrier density and electron mobility of highly doped nanowires are extracted through a combination of transport measurement and Kelvin probe force microscopy analysis in single‐wire field‐effect devices. Low‐temperature photoluminescence is used to characterize the Te‐doped nanowires over several orders of magnitude of the impurity concentration. The combined use of those techniques allows the precise definition of the growth conditions required for effective Te incorporation. 相似文献
The effects of anode/active layer interface modification in bulk‐heterojunction organic photovoltaic (OPV) cells is investigated using poly(3,4‐ethylenedioxythiophene):poly(styrene sulfonate) (PEDOT:PSS) and/or a hole‐transporting/electron‐blocking blend of 4,4′‐bis[(p‐trichlorosilylpropylphenyl)‐phenylamino]biphenyl (TPDSi2) and poly[9,9‐dioctylfluorene‐co‐N‐[4‐(3‐methylpropyl)]‐diphenylamine] (TFB) as interfacial layers (IFLs). Current–voltage data in the dark and AM1.5G light show that the TPDSi2:TFB IFL yields MDMO‐PPV:PCBM OPVs with substantially increased open‐circuit voltage (Voc), power conversion efficiency, and thermal stability versus devices having no IFL or PEDOT:PSS. Using PEDOT:PSS and TPDSi2:TFB together in the same cell greatly reduces dark current and produces the highest Voc (0.91 V) by combining the electron‐blocking effects of both layers. ITO anode pre‐treatment was investigated by X‐ray photoelectron spectroscopy to understand why oxygen plasma, UV ozone, and solvent cleaning markedly affect cell response in combination with each IFL. O2 plasma and UV ozone treatment most effectively clean the ITO surface and are found most effective in preparing the surface for PEDOT:PSS deposition; UV ozone produces optimum solar cells with the TPDSi2:TFB IFL. Solvent cleaning leaves significant residual carbon contamination on the ITO and is best followed by O2 plasma or UV ozone treatment. 相似文献
Ionicity plays an important role in determining material properties, as well as optoelectronic performance of organometallic trihalide perovskites (OTPs). Ion migration in OTP films has recently been under intensive investigation by various scanning probe microscopy (SPM) techniques. However, controversial findings regarding the role of grain boundaries (GBs) associated with ion migration are often encountered, likely as a result of feedback errors and topographic effects common in to SPM. In this work, electron microscopy and spectroscopy (scanning transmission electron microscopy/electron energy loss spectroscopy) are combined with a novel, open‐loop, band‐excitation, (contact) Kelvin probe force microscopy (BE‐KPFM and BE‐cKPFM), in conjunction with ab initio molecular dynamics simulations to examine the ion behavior in the GBs of CH3NH3PbI3 perovskite films. This combination of diverse techniques provides a deeper understanding of the differences between ion migration within GBs and interior grains in OTP films. This work demonstrates that ion migration can be significantly enhanced by introducing additional mobile Cl? ions into GBs. The enhancement of ion migration may serve as the first step toward the development of high‐performance electrically and optically tunable memristors and synaptic devices. 相似文献
The aggressively scaled CMOS technology is increasingly threatening the dependability of network-on-chips (NoCs) architecture. In a mesh-based NoC, a faulty router or broken link may isolate a well functional processing element (PE). Also, a set of faulty routers may form isolated regions, which can degrade the design. In this paper, we propose a router-level redundancy (RLR) fault-tolerant scheme that differs from the traditional microarchitecture-level redundancy (MLR) approach to relieve the problem of isolated PE and isolated region. By simply adding one spare router within each router set in a mesh, RLR can be created and connection paths between adjacent routers can be diversified. To exploit this extra resource, two reconfiguration algorithms are demonstrated to detour observed faulty routers/links. The proposed RLR fault-tolerant scheme can tolerate at most one faulty router within a router set. After the reconfiguration, the original mesh topology is maintained. As a result, the proposed architecture does not need any support from the network layer routing algorithms. The scheme has been evaluated based on the three fault-tolerant metrics: reliability, mean time to failure (MTTF), and yield. The experimental results show that the performance RLR increases as the size of NoC grows; however, the relative connection cost decreases at the same time. This characteristic makes our architecture suitable for large-scale NoC designs.
Low voltage organic field effect memory transistors are demonstrated by adapting a hybrid gate dielectric and a solution processed graphene oxide charge trap layer. The hybrid gate dielectric is composed of aluminum oxide (AlOx) and [8-(11-phenoxy-undecyloxy)-octyl]phosphonic acid (PhO-19-PA) plays an important role of both preventing leakage current from gate electrode and providing an appropriate surface energy to allow for uniform spin-casting of graphene oxide (GO). The hybrid gate dielectric has a breakdown voltage greater than 6 V and capacitance of 0.47 μF/cm2. Graphene oxide charge trap layer is spin-cast on top of the hybrid dielectric and has a resulting thickness of approximately 9 nm. The final device structure is Au/Pentacene/PMMA/GO/PhO-19-PA/AlOx/Al. The memory transistors clearly showed a large hysteresis with a memory window of around 2 V under an applied gate bias from 4 V to −5 V. The stored charge within the graphene oxide charge trap layer was measured to be 2.9 × 1012 cm−2. The low voltage memory transistor operated well under constant applied gate voltage and time with varying programming times (pulse duration) and voltage pulses (pulse amplitude). In addition, the drain current (Ids) after programming and erasing remained in their pristine state after 104 s and are expected to be retained for more than one year. 相似文献