3D Printed Anatomical Nerve Regeneration Pathways

A 3D printing methodology for the design, optimization, and fabrication of a custom nerve repair technology for the regeneration of complex peripheral nerve injuries containing bifurcating sensory and motor nerve pathways is introduced. The custom scaffolds are deterministically fabricated via a microextrusion printing principle using 3D models, which are reverse engineered from patient anatomies by 3D scanning. The bifurcating pathways are augmented with 3D printed biomimetic physical cues (microgrooves) and path‐specific biochemical cues (spatially controlled multicomponent gradients). In vitro studies reveal that 3D printed physical and biochemical cues provide axonal guidance and chemotractant/chemokinetic functionality. In vivo studies examining the regeneration of bifurcated injuries across a 10 mm complex nerve gap in rats showed that the 3D printed scaffolds achieved successful regeneration of complex nerve injuries, resulting in enhanced functional return of the regenerated nerve. This approach suggests the potential of 3D printing toward advancing tissue regeneration in terms of: (1) the customization of scaffold geometries to match inherent tissue anatomies; (2) the integration of biomanufacturing approaches with computational modeling for design, analysis, and optimization; and (3) the enhancement of device properties with spatially controlled physical and biochemical functionalities, all enabled by the same 3D printing process.     

Systematic Doping Control of CVD Graphene Transistors with Functionalized Aromatic Self‐Assembled Monolayers

Recent reports have shown that self‐assembled monolayers (SAMs) can induce doping effects in graphene transistors. However, a lack of understanding persists surrounding the quantitative relationship between SAM molecular design and its effects on graphene. In order to facilitate the fabrication of next‐generation graphene‐based devices it is important to reliably and predictably control the properties of graphene without negatively impacting its intrinsic high performance. In this study, SAMs with varying dipole magnitudes/directions are utilized and these values are directly correlated to changes in performance seen in graphene transistors. It is found that, by knowing the z‐component of the SAM dipole, one can reliably predict the shift in graphene charge neutrality point after taking into account the influence of the metal electrodes (which also play a role in doping graphene). This relationship is verified through density functional theory and comprehensive device studies utilizing atomic force microscopy, X‐ray photoelectron spectroscopy, Raman spectroscopy, and electrical characterization of graphene transistors. It is shown that properties of graphene transistors can be predictably controlled with SAMs when considering the total doping environment. Additionally, it is found that methylthio‐terminated SAMs strongly interact with graphene allowing for a cleaner graphene transfer and enhanced charge mobility.     

Objective distortion measure for binary text image based on edge line segment similarity.

This paper proposes a new approach to measure the distortion introduced by changing individual edge pixels in binary text images. The approach considers not only how many pixels are changed but also where the pixels are changed and how the flipping affects the overall shape formed by the edge line. Similarities between the edge line segments in the original and distorted image are compared to measure the distortion. Subjective testing shows that the new distortion measure correlates well with human visual perception.     

Diindenoperylene derivatives: A model to investigate the path from molecular structure via morphology to solar cell performance

Efficient organic electronic devices require a detailed understanding of the relation between molecular structure, thin film growth, and device performance, which is only partially understood at present. Here, we show that small changes in molecular structure of a donor absorber material lead to significant changes in the intermolecular arrangement within organic solar cells. For this purpose, phenyl rings and propyl side chains are fused to the diindenoperylene (DIP) molecule. Grazing incidence X-ray diffraction and variable angle spectroscopic ellipsometry turned out to be a powerful combination to gain detailed information about the thin film growth. Planar and bulk heterojunction solar cells with C60 as acceptor and the DIP derivatives as donor are fabricated to investigate the influence of film morphology on the device performance. Due to its planar structure, DIP is found to be highly crystalline in pristine and DIP:C60 blend films while its derivatives grow liquid-like crystalline. This indicates that the molecular arrangement is strongly disturbed by the steric hindrance induced by the phenyl rings. The high fill factor (FF) of more than 75% in planar heterojunction solar cells of the DIP derivatives indicates excellent charge transport in the pristine liquid-like crystalline absorber layers. However, bulk heterojunctions of these materials surprisingly result in a low FF of only 54% caused by a weak phase separation and thus poor charge carrier percolation paths due to the lower ordered thin film growth. In contrast, crystalline DIP:C60 heterojunctions lead to high FF of up to 65% as the crystalline growth induces better percolation for the charge carriers. However, the major drawback of this crystalline growth mode is the nearly upright standing orientation of the DIP molecules in both pristine and blend films. This arrangement results in low absorption and thus a photocurrent which is significantly lower than in the DIP derivative devices, where the liquid-like crystalline growth leads to a more horizontal molecular alignment. Our results underline the complexity of the molecular structure-device performance relation in organic semiconductor devices.     

Inkjet printed metallizations for Cu(In1−x Ga x )Se2 photovoltaic cells

This study reports the inkjet printing of Ag front contacts on Aluminum doped Zinc Oxide (AZO)/intrinsic Zinc Oxide (i‐ZnO)/CdS/Cu(In_1−xGa_x)Se₂ (CIGS)/Mo thin film photovoltaic cells. The printed Ag contacts are being developed to replace the currently employed evaporated Ni/Al bi‐layer contacts. Inkjet deposition conditions were optimized to reduce line resistivity and reduce contact resistance to the Al:ZnO layer. Ag lines printed at a substrate temperature of 200°C showed a line resistivity of 2.06 µΩ · cm and a contact resistance to Al:ZnO of 8.2 ± 0.2 mΩ · cm² compared to 6.93 ± 0.3 mΩ · cm² for thermally evaporated contacts. These deposition conditions were used to deposit front contacts onto high quality CIGS thin film photovoltaic cells. The heating required to print the Ag contacts caused the performance to degrade compared to similar devices with evaporated Ni/Al contacts that were not heated. Devices with inkjet printed contacts showed 11.4% conversion efficiency compared to 14.8% with evaporated contacts. Strategies to minimize heating, which is detrimental for efficiency, during inkjet printing are proposed. Copyright © 2011 John Wiley & Sons, Ltd.     

Fault-Tolerant Mesh-Based NoC with Router-Level Redundancy

The aggressively scaled CMOS technology is increasingly threatening the dependability of network-on-chips (NoCs) architecture. In a mesh-based NoC, a faulty router or broken link may isolate a well functional processing element (PE). Also, a set of faulty routers may form isolated regions, which can degrade the design. In this paper, we propose a router-level redundancy (RLR) fault-tolerant scheme that differs from the traditional microarchitecture-level redundancy (MLR) approach to relieve the problem of isolated PE and isolated region. By simply adding one spare router within each router set in a mesh, RLR can be created and connection paths between adjacent routers can be diversified. To exploit this extra resource, two reconfiguration algorithms are demonstrated to detour observed faulty routers/links. The proposed RLR fault-tolerant scheme can tolerate at most one faulty router within a router set. After the reconfiguration, the original mesh topology is maintained. As a result, the proposed architecture does not need any support from the network layer routing algorithms. The scheme has been evaluated based on the three fault-tolerant metrics: reliability, mean time to failure (MTTF), and yield. The experimental results show that the performance RLR increases as the size of NoC grows; however, the relative connection cost decreases at the same time. This characteristic makes our architecture suitable for large-scale NoC designs.

     

A Versatile Fluoro‐Containing Low‐Bandgap Polymer for Efficient Semitransparent and Tandem Polymer Solar Cells

The versatility of a fluoro‐containing low band‐gap polymer, poly[2,6‐(4,4‐bis(2‐ethylhexyl)‐4H‐cyclopenta[2,1‐b;3,4‐b’]dithiophene)‐alt‐4,7‐(5‐fluoro‐2,1,3‐benzothia‐diazole)] (PCPDTFBT) in organic photovoltaics (OPVs) applications is demonstrated. High boiling point 1,3,5‐trichlorobenzene (TCB) is used as a solvent to manipulate PCPDTFBT:[6,6]‐phenyl‐C₇₁‐butyric acid methyl ester (PC₇₁BM) active layer morphology to obtain high‐performance single‐junction devices. It promotes the crystallization of PCPDTFBT polymer, thus improving the charge‐transport properties of the active layer. By combining the morphological manipulation with interfacial optimization and device engineering, the single‐junction device exhibits both good air stability and high power‐conversion efficiency (PCE, of 6.6%). This represents one of the highest PCE values for cyclopenta[2,1‐b;3,4‐b’]dithiophene (CPDT)‐based OPVs. This polymer is also utilized for constructing semitransparent solar cells and double‐junction tandem solar cells to demonstrate high PCEs of 5.0% and 8.2%, respectively.     

Boosting Infrared Light Harvesting by Molecular Functionalization of Metal Oxide/Polymer Interfaces in Efficient Hybrid Solar Cells

Hybrid solar cells based on light absorbing semiconducting polymers infiltrated in nanocrystalline TiO₂ electrodes, have emerged as an attractive concept, combining benefits of both low material and processing costs with well controlled nano‐scale morphology. However, after over ten years of research effort, power conversion efficiencies remain around 0.5%. Here, a spectroscopic and device based investigation is presented, which leads to a new optimization route where by functionalization of the TiO₂ surface with a molecular electron acceptor promotes photoinduced electron transfer from a low‐band gap polymer(poly[2,6‐(4,4‐bis‐(2‐ethylhexyl)‐4H‐cyclopenta[2,1‐b;3,4‐b0]dithiophene)‐alt‐4,7‐(2,1,3‐benzothiadia‐zole)] (PCPDTBT) to the metal oxide. This boosts the infrared response and the power conversion efficiency to over 1%. As a further step, by “co‐functionalizing” the TiO₂ surface with the electron acceptor and an organic dye‐sensitizer, panchromatic spectral photoresponse is achieved in the visible to near‐IR region. This novel architecture at the heterojunction opens new material design possibilities and represents an exciting route forward for hybrid photovoltaics.     

Low operational voltage and high performance organic field effect memory transistor with solution processed graphene oxide charge storage media

Low voltage organic field effect memory transistors are demonstrated by adapting a hybrid gate dielectric and a solution processed graphene oxide charge trap layer. The hybrid gate dielectric is composed of aluminum oxide (AlO_x) and [8-(11-phenoxy-undecyloxy)-octyl]phosphonic acid (PhO-19-PA) plays an important role of both preventing leakage current from gate electrode and providing an appropriate surface energy to allow for uniform spin-casting of graphene oxide (GO). The hybrid gate dielectric has a breakdown voltage greater than 6 V and capacitance of 0.47 μF/cm². Graphene oxide charge trap layer is spin-cast on top of the hybrid dielectric and has a resulting thickness of approximately 9 nm. The final device structure is Au/Pentacene/PMMA/GO/PhO-19-PA/AlO_x/Al. The memory transistors clearly showed a large hysteresis with a memory window of around 2 V under an applied gate bias from 4 V to −5 V. The stored charge within the graphene oxide charge trap layer was measured to be 2.9 × 10¹² cm⁻². The low voltage memory transistor operated well under constant applied gate voltage and time with varying programming times (pulse duration) and voltage pulses (pulse amplitude). In addition, the drain current (I_ds) after programming and erasing remained in their pristine state after 10⁴ s and are expected to be retained for more than one year.