Social‐based reputation‐aware data forwarding for improved multicast delivery in the presence of selfish nodes in DTNs

Delay/disruption tolerant networks (DTNs) are potentially applicable in the challenged scenarios like post‐disaster environments. In such networks, data forwarding generally relies on the mutual cooperation of the nodes. However, in reality, despite the availability of necessary resources for data forwarding, a node could misbehave by dropping messages received from other nodes with whom it has no strong social ties. Such a node is called a socially selfish node, which would cause a poor delivery ratio in the network. In this paper, we aim to address the problem of multicast data forwarding in the presence of such selfish nodes, by means of efficient relay selection in DTNs. First, we define a realistic reputation model, in contrast to existing models, to define the socially selfish/misbehaving nodes in the network. Further, a game‐theoretic analysis is carried out that implies data forwarding cost is also an influential parameter in handling selfishness/misbehavior. Subsequently, the problem is formulated as a constrained optimization problem, which is NP hard. Therefore, a heuristic is proposed by combining the reputation of a node and the cost of message forwarding to appropriately identify relay nodes, thus improve the performance of the multicast message delivery in the network. We utilize a social metric, centrality to minimize the message forwarding cost in terms of the number of relay nodes. Finally, the comparative performance evaluation in ONE simulator with practical scenarios shows the superiority of the proposed scheme over the other prominent schemes.     

Encrypted Network Traffic Classification and Resource Allocation with Deep Learning in Software Defined Network

Wireless Personal Communications - The climate has changed absolutely in every area in just a few years as digitized, making high-speed internet service a significant need in the future. Future...     

Location Update versus Paging Trade-Off in Cellular Networks: An Approach Based on Vector Quantization

In this paper, we propose two information-theoretic techniques for efficiently trading off the location update and paging costs associated with mobility management in wireless cellular networks. Previous approaches always attempt to accurately convey a mobile's movement sequence and hence cannot reduce the signaling cost below the entropy bound. Our proposed techniques, however, exploit the rate distortion theory to arbitrarily reduce the update cost at the expense of an increase in the corresponding paging overhead. To this end, we describe two location tracking algorithms based on spatial quantization and temporal quantization, which first quantize the movement sequence into a smaller set of codewords and then report a compressed representation of the codeword sequence. Although the spatial quantization algorithm clusters individual cells into registration areas, the more powerful temporal quantization algorithm groups sets of consecutive movement patterns. The quantizers themselves are adaptive and periodically reconfigure to accommodate changes in the mobile's movement pattern. Simulation study with synthetic and real movement traces for both single-system and multisystem cellular networks demonstrate that the proposed algorithms can reduce the mobile's update frequency to 3-4 updates/day with reasonable paging cost, low computational complexity, storage overhead, and codebook updates.     

Vertically integrated SOI circuits for low-power and high-performance applications

Vertical integration offers numerous advantages over conventional structures. By stacking multiple-material layers to form double gate transistors and by stacking multiple device layers to form multidevice-layer integration, vertical integration can emerge as the technology of choice for low-power and high-performance integration. In this paper, we demonstrate that the vertical integration can achieve better circuit performance and power dissipation due to improved device characteristics and reduced interconnect complexity and delay. The structures of vertically integrated double gate (DG) silicon-on-insulator (SOI) devices and circuits, and corresponding multidevice-layer (3-D) SOI circuits are presented; a general double-gate SOI model is provided for the study of symmetric and asymmetric SOI CMOS circuits; circuit speed, power dissipation of double-gate dynamic threshold (DGDT) SOI circuits are investigated and compared to single gate (SG) SOI circuits; potential 3-D SOI circuits are laid out. Chip area, layout complexity, process cost, and impact on circuit performance are studied. Results show that DGDT SOI CMOS circuits provide the best power-delay product, which makes them very attractive for low-voltage low-power applications. Multidevice-layer integration achieves performance improvement by shortening the interconnects. Results indicate that up to 40% of interconnect performance improvements can be expected for a 4-device-layer integration.     

Photonic bandgap fibre oscillators and amplifiers

In the search for ever higher output power or energy from fibre oscillators or amplifiers a nowadays mature technology relies on enlarging the fibre mode area. Broadening of the core diameter, all other things being equal, inevitably yields a multimode fibre, thereby dramatically limiting the device usefulness. Various strategies have been deployed to design and manufacture single transverse mode fibre oscillators and amplifiers, among which making use of the so-called photonic bandgap effect to restrict the modal population seems promising. Helped by efficient and reliable numerical tools the design of large mode area singlemode photonic bandgap fibres is presented. Two fibres with 20-μm and 40-μm core diameter, both of them heavily doped with Yb³⁺ ions, have been fabricated by the widespread modified chemical vapour deposition process and are shown to behave properly when used as the core element of either continuous wave oscillators or femtosecond amplifiers. Good output beam quality (M² parameter spanning from 1.12 to 1.5 for the set of fibres studied) and high slope efficiency of 80% in cw oscillation regime are demonstrated. Furthermore the 40-μm core diameter fibre is shown to be resilient to tight bending down to 7.5-cm radius. The stack-and-draw process makes it easy to tailor the outer cladding so that a large numerical aperture can be reached. Subsequently, from this air-clad fibre, 500 fs 47 W pulses at 35 MHz are obtained from a two-stage chirped pulse amplification system.     

Subspace blind adaptive detection for multiuser CDMA

Direct adaptive realizations of the linear minimum mean-square error (MMSE) receiver for direct-sequence code-division multiple access possess the attractive feature of not requiring any explicit information of interference parameters such as timing, amplitudes, or spreading sequences; however, they need a training sequence for the desired user. Previously, a new blind adaptive receiver was proposed based on an anchored least mean-squared (LMS) algorithm that requires only the spreading code and symbol timing of the desired user but obviates the need for a training sequence. In this work, it is analytically demonstrated that the blind LMS algorithm always provides (nominally) faster convergence than the training driven LMS-MMSE receiver of but at the cost of increased tap-weight fluctuations or misadjustment. Second, the property that the optimal MMSE or minimum-output energy filter coefficients lies in the signal subspace is exploited to propose a new efficient blind adaptive receiver requiring fewer adaptive coefficients. Improved detector characteristics (superior convergence rates and steady-state signal-to-interference-plus-noise ratios) is indicated by analysis and supported by simulation     

O/sup 2/ABA: a novel high-performance predictable circuit architecture for the deep submicron era

Current VLSI design techniques focus on four major goals: higher integration, faster speed, lower power, and shorter time-to-market. These goals have been accomplished mainly by deep submicron (DSM) technology along with voltage scaling. However, scaling down of feature size causes larger interwire capacitance which results in large crosstalk between interconnects. In this paper, we propose a novel predictable circuit architecture, named "optimized overlaying array-based architecture" (O/sup 2/ABA), especially suited for the deep submicron regime. O/sup 2/ABA achieves reduction in crosstalk by considering the current directions and by reducing interwire capacitance. The introduction of "unit cell" leads to regularity, which makes the performance predictable even before layout, and shortens design time. O/sup 2/ABA is compared with other design styles, such as custom design and standard cell approach, in terms of coupling capacitance, area, and delay.