Nanostructured α/β-tungsten by reduction of WO3 under microwave plasma

The formation of tungsten by microwave plasma induced reduction of coarse grade, crystalline (monoclinic and hexagonal blend) WO₃ was investigated. It was observed that nanostructured α-W (cubic; space group: Im-3m) as well as β-W (cubic, space group: Pm-3n) are present in the final product. The fraction of β-W was higher (56 (± 3) wt.%) when compared to α-W (41 (± 4) wt.%). The high resolution scanning electron microscopy revealed narrow size distribution of the as synthesized tungsten with average particle size of about 10-25 nm. The estimated crystallite sizes from the log-normal size distribution obtained from the Warren-Averbach's Fourier treatment of the XRD profile were about 12 (± 3) and 15 (± 2) nm for α and β-W, respectively. The observed particle/crystallite sizes were significantly finer when compared to conventional plasma synthesized tungsten due to lower processing temperature in microwave plasma synthesis technique.     

Heat convection length for boundary-layer flows

In analyses of heat convection problems, it is traditional to introduce the heat transfer coefficient, h, such that the average heat flux at the solid surface can be conveniently calculated. To find h, one has to simultaneously solve governing equations for conservations of mass, momentum, and energy. This task may prove too challenging for contemporary undergraduate students. In the present study, we propose a heat convection length, Δs, which can greatly simplify the analysis, yet allow the convection characteristics to be retained. Classical examples for laminar boundary-layer air flows driven by forced convection or free convection over flat plates with length L are presented. For forced convection, Δs/L is found to be 2.026 for a wide range of Re; for free convection, Δs/L is found to be 2.511 for various Gr values.     

RZ-DPSK transmission using a 42.7-Gb/s integrated balanced optical front end with record sensitivity

We have demonstrated a record sensitivity of -37.0 dBm (38 photons/bit) for a BER of 10/sup -9/ at 42.7-Gb/s using an integrated balanced optical front end. Results were obtained using optical preamplification of RZ-DPSK modulation and an external delay-interferometer. The OSNR requirement was measured to be 16.9 dB in a 0.1-nm bandwidth. The impact of polarization-mode dispersion (PMD) and chromatic dispersion on the optical front end performance has been measured. Performance for enhanced forward error correction has been projected based on 10/sup -3/ BER performance.     

Demonstration of enhanced performance of an InP/InGaAsheterojunction phototransistor with a base terminal

The optical gain and the small-signal frequency response of an InP/InGaAs heterojunction phototransistor (HPT) with a base terminal are investigated in detail for the first time. When operated under an optimally chosen external base current, the optical gain is enhanced more than five times over that of the same device operated as a two-terminal device, over a 17-dB range of input optical power. The small-signal 3-dB bandwidth of the three-terminal device is enhanced 15 times over that of the two-terminal device over the same range of input optical power. For a pseudorandom NRZ bit stream at 100 Mb/s, a clear eye opening is observed at an incident optical power of -33 dBm (500 nW)     

A parallel polygon-clipping algorithm

We describe a new parallel polygonclipping algorithm based on a novel technique that allows a processor to compute output vertices independently of the results of the other processors. The basis for the method is a collision-free labeling scheme to compute the labels of the vertices of the output polygon. This labeling scheme depends only on the id of the vertices of the output polygon. This labeling scheme depends only on the id of the vertex in the input polygon. This procedure allows us to defer the synchronization between processors to the final stages of the algorithm, reduces the amount of overhead due to fine-grain synchronization, and helps makes the algorithm efficient.     

Tunable dispersion compensation at 40-Gb/s using a multicavity etalon all-pass filter with NRZ, RZ, and CS-RZ modulation

We present a multichannel tunable dispersion compensator (TDC) based on multicavity all-pass etalons that is capable of operation at 40 Gb/s. The device has a tuning range of +200/-220 ps/nm with a group delay ripple < /spl plusmn/5 ps over a channel bandwidth of 80 GHz, an overall loss of < 5.2 dB, very low insertion loss ripple, and can operate on any channel on a 200-GHz grid over the C-band. In addition, we present system performance results at 40 Gb/s using NRZ, RZ, and CS-RZ modulation, compensating up to 45 km of nonzero dispersion shifted fiber (NZDSF). Our results show that this device introduces very little excess system penalty with signal frequency drifts of up to 20 GHz when operated near the center of its tuning range. For single channel experiments with fiber, the system penalty increase versus signal detuning is more significant, but can be reduced by dynamically optimizing the device dispersion during detuning. Finally, we demonstrate simultaneous compensation of 4 channels across the C-band over 25 km of NZDSF.     

Modeling and characterization of the polymer stud grid array (PSGA) package: electrical, thermal and thermo-mechanical qualification

We characterize the polymer stud grid array (PSGA) package electrically, thermally and thermo-mechanically for successful commercial application. For the electrical characterization, we extract lumped parameter resistance-inductance-capacitance (RLC) models for the interconnects from simulations. We also measure the RF performance of the package on printed circuit board (PCB) test structures. The average self-inductance from the wirebond pad to the bottom of the stud is 0.53 nH and the total capacitance to the ground is 0.26 pF for an interconnection of the periphery of the over the edge (OTE) type PSGA. The lumped RLC model is verified by full three-dimensional (3-D) EM simulations. Simulation models also indicate that the "Micro-via" (/spl mu/-via) type of interconnection on the PSGA package improves performance by decreasing the inductance on an average by 60%. Thermal characterization involves the development of a steady-state thermal compact model with six nodes for the 72-pin PSGA. We also perform transient thermal measurements on test packages to fine-tune the detailed model. For the thermo-mechanical case we test the first level and second level reliability by experiments and optimize them using simulations. The board level reliability for the 72-pin PSGA mounted on a PCB is very high (N50%>10000 cycles). Simulations also show a higher reliability for the PSGA than the plastic ball grid array (PBGA).