A Novel Test Point Selection Method for Analog Fault Dictionary Techniques

Most of the recently reported test point selection algorithms for analog fault dictionary techniques are based on integer-coded table (ICT) technique. Hence, the accuracy of these algorithms is closely related to the accuracy of the ICT technique. Unfortunately, this technique is not accurate, especially when the size of fault dictionary is large. This paper proposes an accurate fault-pair Boolean table technique for the test point selection problem. First, the approach to transform the fault dictionary into a fault-pair Boolean table is introduced. Then, a test point selection algorithm based on the fault-pair Boolean table is proposed. Thirdly, several example circuits are used to illustrate the proposed algorithm. Simulated results indicate that the proposed method is more accurate than the other methods. Therefore, it is a good solution for minimizing the size of the test point set.     

Measurement of RF Transmission Mode in ITER Relevant EC H&;CD Transmission Line

The preliminary results of mode measurement in the ITER relevant 40 m long transmission test line composed from 63.5 mm diameter corrugated waveguides and miter bends are presented. The field patterns were measured by taking temperature profiles on a paper screen placed in front of the waveguide end using an infrared imaging camera. The complex electric field at the waveguide end was retrieved from the measured temperature profiles. As a result, the transmission power includes 87% of HE₁₁ mode and 6% of LP₁₁ odd (HE₂₁+TE₀₁) mode and small ratios of other modes. The mode content had small dependence on length of the transmission line. This result indicated that the higher order mode content generated at the input of the transmission line is conserved and propagated through the transmission line. This suggests that the initial RF coupling to the waveguide is critical since it affects the launcher efficiency.     

Non-fragile <Emphasis Type="Italic">H</Emphasis><Subscript>2</Subscript> and <Emphasis Type="Italic">H</Emphasis><Subscript>∞</Subscript> filter designs for polytopic two-dimensional systems in Roesser model

This paper is concerned with the problem of non-fragile H ₂ and H _∞ filter designs for two-dimensional (2-D) discrete systems in Roesser model with polytopic uncertainties. The filters to be designed are assumed to be with additive norm-bounded coefficient variations which reflect the imprecision in filter implementation. The complicated filter design problem is successfully tackled by using the slack variable technique and imposing a structural restriction on the slack matrix. Explicit expressions of the non-fragile H ₂ and H _∞ filters are given in terms of solutions to a set of linear matrix inequalities (LMIs). An illustrative example is provided to demonstrate the feasibility and effectiveness of the proposed method.     

Growth of Epitaxial (110) 0.7Pb(Mg<Subscript>1/3</Subscript>Nb<Subscript>2/3</Subscript>)O<Subscript>3</Subscript>-0.3PbTiO<Subscript>3</Subscript> Thin Films on r-Plane Sapphire Substrates by RF Magnetron Sputtering

The role of substrate temperature and substrate surface geometry in determining the crystal structure and crystallinity of 0.7Pb(Mg_1/3Nb_2/3)O₃-0.3PbTiO₃ (PMN-PT) thin films grown on r-plane sapphire substrates is examined. A 30-nm-thick amorphous PMN-PT seed layer deposited at 250°C and subjected to rapid thermal annealing at 850°C results in the formation of an epitaxial (110) perovskite PMN-PT growth template that can be used for subsequent growth of single-crystal (110) perovskite PMN-PT films at elevated temperature. The data show that single-crystal perovskite is promoted when the films nucleate with the \( \langle \overline{1} 11 \rangle \) PMN-PT direction parallel to the \( \langle 0\bar{2}21 \rangle \) Al₂O₃ direction.     

A new call control scheme of Push-To-Talk system

For Push-To-Talk (PTT) system based on Public Mobile Data Network (PMDN), the end-to-end time delay is the key aspect of the user’s experience. The Push-Over-Cellular (POC) scheme defined by Open Mobile Alliance (OMA) is based on the VoIP phone model and use SIP protocol as the call control scheme. The call setup time delay in SIP may reach to several seconds, which is unacceptable for the PTT service. In this paper, we provide a new call control scheme for PTT system based on PLMN network. By combining the apriority knowledge of PTT call model and the priority control scheme, we encapsulate the signaling message and the voice data into a same data packet, when the user push the button, the voice and the call control signaling are sent to the server at the same time. So the long time delay of call setup procedure of POC scheme can be eliminate. The end-to-end call delay can be decreased significantly. The experiment result based on the commercial CDMA2000 1X network of China Unicom shows that the call delay can be decreased to 600 ms, which approach to the traditional trunk communication system’s requirement.     

A high performance CNFET-based operational transconductance amplifier and its applications

High performance electronic systems face several challenges in driving innovative integrated circuits when the internal transistors are scaled down below 45 nm. Carbon nanotube field effect transistors (CNFETs) are considered as excellent candidates for building energy-efficient electronic systems in the near future, due to their unique characteristics such as ballistic transport, scalability, and better channel electrostatics. In this paper, a new high performance operational transconductance amplifier (OTA) based on 32 nm CNFET devices is presented. The proposed OTA maintains a highly linear wide continuous tuning range and a wide frequency response range, enabled by splitting the linear voltage-to-current conversion and tuning two different blocks. As an application, a universal second-order transconductance-capacitor (G _m  ? C) filter realized using the OTA is introduced. Simulation results show that the CNFET-based OTA offers very a low current consumption of 2.35 μA from a ± 0.9 V power supply, achieves a bandwidth of 9.5 MHz, and has an input dynamic range of ± 0.2 V.     

Design of 0.5 V voltage-combiner based OTA with 60 dB gain 250 kHz UGB in CMOS

A gain enhancement technique for a pseudo differential OTA based on voltage combiner, suitable for sub-1 V supply is presented in this letter. The proposed technique uses a G _m boosted voltage combiner. Unlike the typical voltage combiner which has an approximated gain of \(2\,\frac{{\text{V}}}{{\text{V}}}\), this voltage combiner can produce gain more than \(5\,\frac{{\text{V}}}{{\text{V}}}\). So it help us achieve nearly 60 dB DC gain with 250 kHz UGB for the pseudo differential OTA at a capacitive load of 10 pF. Power dissipation is very low i.e. 716 nW at supply of 0.5 V. So as to facilitate maximum swing at 0.5 V supply and lower the power consumption, MOS transistors are biased in weak/moderate inversion. The OTA is designed in standard 45 nm CMOS process. Phase margin of is more than \(55^{\circ }\) for a typical load of 10 pF. The input referred noise is \(150\,\upmu {\text{V}}{/}\sqrt{{\text{Hz}}}\) at 10 Hz and slew rate \(0.02\,{\text{V}}{/}\upmu{\text{s}}\) for 10 pF load.     

A Class of Sequential Blind Source Separation Method in Order Using Swarm Optimization Algorithm

We consider the problem of sequential, blind source separation in some specific order from a mixture of sub- and sup-Gaussian sources. Three methods of separation are developed, specifically, kurtosis maximization using (a) particle swarm optimization, (b) differential evolution, and (c) artificial bee colony algorithm, all of which produce the separation in decreasing order of the absolute kurtosis based on the maximization of the kurtosis cost function. The validity of the methods was confirmed through simulation. Moreover, compared with other conventional methods, the proposed method separated the various sources with greater accuracy. Finally, we performed a real-world experiment to separate electroencephalogram (EEG) signals from a super-determined mixture with Gaussian noise. Whereas the conventional methods separate simultaneously EEG signals of interest along with noise, the result of this example shows the proposed methods recover from the outset solely those EEG signals of interest. This feature will be of benefit in many practical applications.     

CaPPS: cache partitioning with partial sharing for multi-core embedded systems

As the number of cores in chip multi-processor systems increases, the contention over shared last-level cache (LLC) resources increases, thus making LLC optimization critical, especially for embedded systems with strict area/energy/power constraints. We propose cache partitioning with partial sharing (CaPPS), which reduces LLC contention using cache partitioning and improves utilization with sharing configuration. Sharing configuration enables the partitions to be privately allocated to a single core, partially shared with a subset of cores, or fully shared with all cores based on the co-executing applications’ requirements. CaPPS imposes low hardware overhead and affords an extensive design space to increase optimization potential. To facilitate fast design space exploration, we develop an analytical model to quickly estimate the miss rates of all CaPPS configurations using the applications’ isolated LLC access traces to predict runtime LLC contention. Experimental results demonstrate that the analytical model estimates cache miss rates with an average error of only 0.73 % and with an average speedup of \(3505\times \) as compared to a cycle-accurate simulator. Due to CaPPS’s extensive design space, CaPPS can reduce the average LLC miss rate by as much as 25 % as compared to baseline configurations and as much as 14–17 % as compared to prior works.     

A Power Efficient Test Data Compression Method for SoC using Alternating Statistical Run-Length Coding

A power efficient System-on-a-Chip test data compression method using alternating statistical run-length coding is proposed. To effectively reduce test power dissipation, the test set is firstly preprocessed by 2D reordering scheme. To further improve the compression ratio, 4 m partitioning of the runs and a smart filling of the don’t care bits provide the nice results, and alternating statistical run-length coding scheme is developed to encode the preprocessed test set. In addition, a simple decoder is obtained which consumed a little area overhead. The benchmark circuits verify the proposed power efficient coding method well. Experimental results show it obtains a high compression ratio, low scan-in test power dissipation and little extra area overhead during System-on-a-Chip scan testing.