A Multiple-Rate, Multicarrier Direct-Sequence CDMA System with 2-D OVSF Codes in Fading Channels

In this paper, a multiple-rate, multicarrier direct- sequence code-division multiple-access (MC/DS-CDMA) system with the use of two-dimensional orthogonal variable spreading factor (2-D OVSF) codes is studied. They are the first 2-D codes that can be generated by the tree structure commonly used by one-dimensional OVSF codes in wideband-CDMA. The 2-D OVSF codes also preserve orthogonality among code matrices with different spreading factors in the code tree. The performances of the proposed system with RAKE receivers employing equal-gain and maximal-ratio combining methods are analyzed and compared. Our results show that our multiple-rate MC/DS-CDMA system with the 2-D OVSF codes is more suitable for a non-fading additive white Gaussian noise channel or a Rician weak-fading channel. However, in a Rayleigh fading channel, the system performance gets worse because the orthogonality of the 2-D OVSF codes is destroyed by the strong fading effect.     

Comparison of self‐adaptive dynamic differential evolution and particle swarm optimization for smart antennas in wireless communication

In this paper, ultrawide band (UWB) communication systems with eight transmitting and receiving ring antenna arrays are implemented to test the bit error rate and capacity performance. By using the ray‐tracing technique to compute any given indoor wireless environment, the impulse response of the system can be calculated. The synthesized beamforming problem can be reformulated into a multiobjective optimization problem. Self‐adaptive dynamic differential evolution (SADDE) and particle swarm optimization (PSO) are used to find the excitation current and the feed line length of each antenna to form the appropriate beam pattern. This pattern can then reduce the bit error rate and increase the channel capacity and receiving energy. Numerical results show that the fitness value and the convergence speed by the SADDE are better than those by the PSO. Moreover, the SADDE had better results for both line‐of‐sight and nonline‐of‐sight cases. In other words, compared with PSO, SADDE has improved more effectively the main beam radiation energy and reduced the multipath interference.     

Electric fields in bone marrow substructures at power-line frequencies

Bone marrow is known to be responsible for leukemia. In order to study the hypothesis relating power-line frequencies electromagnetic fields and childhood leukemia from a subcellular perspective, two models of bone marrow substructures exposed to electric field are computed numerically. A set of cancellous bone data obtained from computed tomography scan is computed using both the finite element method (FEM) and scalar potential finite difference method. A maximum electric field enhancement of 50% is observed. Another model of bone marrow stroma cells is implemented only in FEM using thin film approximation. The transmembrane potential (TMP) change across the gap junctions is found to range from several to over 200 microV. The two results suggest that imperceptible contact currents can produce biologically significant TMP change at least in a limited number of bone marrow stroma cells.     

InGaAs and Ge MOSFETs with high κ dielectrics

InGaAs and Ge MOSFETs with high κ’s are now the leading candidates for technology beyond the 15 nm node CMOS. The UHV-Al₂O₃/Ga₂O₃(Gd₂O₃) [GGO]/InGaAs has low electrical leakage current densities, C-V characteristics with low interfacial densities of states (D_it’s) and small frequency dispersion in both n- and p-MOSCAPs, thermal stability at temperatures higher than >850 °C, a CET of 2.1 nm (a CET of 0.6 nm in GGO), and a well tuning of threshold voltage V_th with metal work function. Device performances in drain currents of >1 mA/μm, transconductances of >710 μS/μm, and peak mobility of 1600 cm²/V s at 1 μm gate-length were demonstrated in the self-aligned, inversion-channel high In-content InGaAs n-MOSFETs using UHV-Al₂O₃/GGO gate dielectrics and ALD-Al₂O₃. Direct deposition of GGO on Ge without an interfacial passivation layer has given excellent electrical performances and thermodynamic stability. Self-aligned Ge p-MOSFETs have shown a high drain current of 800 μA/μm and peak transconductance of 420 μS/μm at 1 μm gate-length.     

Novel GaAs enhancement-mode/depletion-mode pHEMTs technology using high-k praseodymium oxide interlayer

In this study, a novel metal–semiconductor gate enhancement-mode (E-mode) and a metal–insulator-metal–semiconductor (MIMS) gate depletion-mode (D-mode) AlGaAs/InGaAs pseudomorphic high electron mobility transistor (pHEMT) on a single GaAs substrate have been developed by using high dielectric constant praseodymium insulator layer. The epitaxial layers were design for an enhancement-mode pHEMT after gate recess process. To achieve E/D-mode pHEMTs on single GaAs wafer, traditional Pt/Ti/Au metals were deposited as Schottky contact for E-mode pHEMTs and Pr/Pr₂O₃/Ti/Au were deposited as MIMS-gate for D-mode pHEMTs. This AlGaAs/InGaAs E-mode pHEMTs exhibit a gate turn-on voltage (V_ON) of +1 V and a gate-to-drain breakdown voltage of ?5.6 V, and these values were +7 V and ?34 V for MIMS-gate D-mode pHEMTs, respectively. Therefore, this high-k insulator in D-mode pHEMT is beneficial for suppressing the gate leakage current. Comparing to previous E/D-mode pHEMT technology, this E-mode pHEMTs and MIMS-gate D-mode pHEMTs exhibit a highly potential for high uniformity GaAs logic circuit applications due to its single recess process.     

Fault-Tolerant Mesh-Based NoC with Router-Level Redundancy

The aggressively scaled CMOS technology is increasingly threatening the dependability of network-on-chips (NoCs) architecture. In a mesh-based NoC, a faulty router or broken link may isolate a well functional processing element (PE). Also, a set of faulty routers may form isolated regions, which can degrade the design. In this paper, we propose a router-level redundancy (RLR) fault-tolerant scheme that differs from the traditional microarchitecture-level redundancy (MLR) approach to relieve the problem of isolated PE and isolated region. By simply adding one spare router within each router set in a mesh, RLR can be created and connection paths between adjacent routers can be diversified. To exploit this extra resource, two reconfiguration algorithms are demonstrated to detour observed faulty routers/links. The proposed RLR fault-tolerant scheme can tolerate at most one faulty router within a router set. After the reconfiguration, the original mesh topology is maintained. As a result, the proposed architecture does not need any support from the network layer routing algorithms. The scheme has been evaluated based on the three fault-tolerant metrics: reliability, mean time to failure (MTTF), and yield. The experimental results show that the performance RLR increases as the size of NoC grows; however, the relative connection cost decreases at the same time. This characteristic makes our architecture suitable for large-scale NoC designs.

     

Data Center Switch for Load Balanced Fat-Trees

With the growing of cloud computing, the need of computing power no longer can be satisfied with a few powerful servers or small scale parallel computer systems. More and more servers are connected together as a data center network. Then, fault tolerance becomes an import issue when building a massive data center network. Currently, many researches focus on building fat-tree data center networks. In this paper, we propose a load balanced fat-tree architecture with uniform mapping connection patterns to provide higher fault tolerance capability for heavy traffic load networks. Two fault tolerated 4 × 4 banyan type switch designs are introduced to improve the fault tolerance capability of fat-tree networks. Finally, fault tolerance capability evaluations of link or switch faults in fat-tree network are given to support our idea, and a 4 × 4 banyan type switch IC is demonstrated as the commodity switch for building the fault tolerant fat-tree data center networks. The 4 × 4 banyan type switch IC is fabricated in 90 nm CMOS technology, and the maximum operation rate of the IC is 5.8 Gbps per channel or 23.2 Gbps total data rate with only 23 ps peak-to-peak jitter.     

Metal‐Free Growth of Nanographene on Silicon Oxides for Transparent Conducting Applications

Conventional methods to prepare large‐area graphene for transparent conducting electrodes involve the wet etching of the metal catalyst and the transfer of the graphene film, which can degrade the film through the creation of wrinkles, cracks, or tears. The resulting films may also be obscured by residual metal impurities and polymer contaminants. Here, it is shown that direct growth of large‐area flat nanographene films on silica can be achieved at low temperature (400 °C) by chemical vapor deposition without the use of metal catalysts. Raman spectroscopy and TEM confirm the formation of a hexagonal atomic network of sp²‐bonded carbon with a domain size of about 3–5 nm. Further spectroscopic analysis reveals the formation of SiC between the nanographene and SiO₂, indicating that SiC acts as a catalyst. The optical transmittance of the graphene films is comparable with transferred CVD graphene grown on Cu foils. Despite the fact that the electrical conductivity is an order of magnitude lower than CVD graphene grown on metals, the sheet resistance remains 1–2 orders of magnitude better than well‐reduced graphene oxides.     

High performance BCB-bridged AlGaAs/InGaAs power HFETs

A novel low-k benzocyclobutene (BCB) bridged and passivated layer for AlGaAs/InGaAs doped-channel power field effect transistors (FETs) with high reliability and linearity has been developed and characterized. In this study, we applied a low-k BCB-bridged interlayer to replace the conventional air-bridged process and the SiN/sub x/ passivation technology of the 1 mm-wide power device fabrication. This novel and easy technique demonstrates a low power gain degradation under a high input power swing, and exhibits an improved adjacent channel power ratio (ACPR) than those of the air-bridged one, due to its lower gate leakage current. The power gain degradation ratio of BCB-bridged devices under a high input power operation (P/sub in/ = 5 /spl sim/ 10 dBm) is 0.51 dB/dBm, and this value is 0.65 dB/dBm of the conventional air-bridged device. Furthermore, this novel technology has been qualified by using the 85-85 industrial specification (temperature = 85 C, humidity = 85%) for 500 h. These results demonstrate a robust doped-channel HFET power device with a BCB passivation and bridged technology of future power device applications.