Implementation of a self-timed segmented bus

We propose an asynchronous structure for implementation on a SoC. An intersegment topological arrangement preserves parallelization and, through a so-called central arbiter, efficiently organizes communication with high signaling speed in the proposed structure. Researchers proposed the concept of segmenting buses primarily for multicomputer architectures. More recent approaches address on-chip implementation of segmented buses. We present an asynchronous segmented-bus architecture targeted for the modular design of high-performance SoC applications. The structure not only enables faster operation than a conventional bus system but also offers lower power consumption per transferred data item. This is possible because segmentation is realized in such a way that the majority of data transfers in the system are intrasegment transactions on relatively short wires with low or moderate capacitive loads.     

A Distributed State Estimator Utilizing Synchronized Phasor Measurements

With the creation of balancing authorities by the North American Reliability Council that span large portions of the North American interconnection, and stringent requirements for real time monitoring of power system evolution, faster and more accurate state estimation algorithms that can efficiently handle systems of very large sizes are needed in the present environment. This paper presents a distributed state estimation algorithm suitable for large-scale power systems. Synchronized phasor measurements are applied to aggregate the voltage phase angles of each decomposed subsystem in the distributed state estimation solution. The aggregated state estimation solution is obtained from the distributed solution using a sensitivity analysis based update at chosen boundary buses. Placement of synchronized phasor measurements in the decomposed subsystems is also investigated in this paper. Test results on the IEEE 118-bus test bed are provided     

An Adaptive Recipe Implementation in Case‐Based Formalism for Abnormal Condition Management

This paper deals with accurate recipe implementation for abnormal condition management in a batch process using a case‐based reasoning (CBR) approach. A set of new problems can be solved by reusing proven process solutions. The proposed system integrates quantitative and qualitative parameters for adaptation of cases. A novel methodology to generate accurate recipes and to adapt to the processes is introduced during normal and abnormal conditions. In particular, the differences between current conditions and the references (recipes) should be managed to prevent any hazardous conditions arising. The processes are evaluated using their similarity to the past cases. This intelligent approach distinguishes plausible cases, generates accurate recipes, and adapts to new situations. The aim is to use the offline historical process data and safety related information in order to propose changes and adjustments in the processes.     

Cooling and Solidification of Melted Drops in an Immiscible Cooling Medium

The cooling and solidification of melted drops during their movement in an immiscible cooling medium is widely employed for granulation in the chemical industry, and a study of these processes to provides a basis for the design of the granulation tower height and the temperature of the cooling medium is reported. A physical model of the cooling and solidification of the drop is established and the numerical calculation is performed. The influences of the key factors in the solidification, i.e., Bi number, drop diameter, temperature of the cooling medium, etc. are presented. The cooling and solidification during wax granulation in a water‐cooling tower and during urea granulation in an air‐cooling tower (spraying tower) are described in detail. Characteristics of the solidification and temperature distribution within the particle at different times are shown. The model and calculations can be used for structure design of the granulation tower and optimization of the operation parameters.     

Evaluation of ProKappa

ProKappa is an expert system tool kit developed by IntelliCorp in C using X-Windows for graphical interface. The SUN 3 or 4 version costs $9995/£7000 and $2595/£1800 for the interactive C environment.
This review covers ProKappa version 1.1, installed on a colour SUN SPARC Station 1 with the minimum recommended values of 12 Mb of memory and 30 Mb of swap space.
IntelliCorp can be contacted in the USA at 1975 El Camino Real West, Mountain View, CA 94040-2216 (+1 (415) 965-5500) and in the UK at 10 Jewry Street, Winchester, Hampshire SO23 8RZ (+44 (0)962 735348).