Covariance Structure Maximum-Likelihood Estimates in Compound Gaussian Noise: Existence and Algorithm Analysis

Recently, a new adaptive scheme [Conte (1995), Gini (1997)] has been introduced for covariance structure matrix estimation in the context of adaptive radar detection under non-Gaussian noise. This latter has been modeled by compound-Gaussian noise, which is the product c of the square root of a positive unknown variable tau (deterministic or random) and an independent Gaussian vector x, c=radictaux. Because of the implicit algebraic structure of the equation to solve, we called the corresponding solution, the fixed point (FP) estimate. When tau is assumed deterministic and unknown, the FP is the exact maximum-likelihood (ML) estimate of the noise covariance structure, while when tau is a positive random variable, the FP is an approximate maximum likelihood (AML). This estimate has been already used for its excellent statistical properties without proofs of its existence and uniqueness. The major contribution of this paper is to fill these gaps. Our derivation is based on some likelihood functions general properties like homogeneity and can be easily adapted to other recursive contexts. Moreover, the corresponding iterative algorithm used for the FP estimate practical determination is also analyzed and we show the convergence of this recursive scheme, ensured whatever the initialization.     

Stability and 2-D Simulation Studies of Avalanche Breakdown in 4H-SiC DMOSFETs With JTE

In this paper, the stability of n-channel 4H-silicon carbide (SiC) DMOSFETs with junction termination extension (JTE) was assessed by measuring the breakdown voltage (BV) of these devices before and after bias stress at a high temperature. The BV slumped after the DMOSFET was bias stressed at 1200 V for 2 h at 175degC, and the slumped BV dynamically recovered to the prestress value during the poststress period. Computer simulation suggests that the BV slump and its recovery are dominated by the positive charge trapping/detrapping phenomena at the SiC/fleld oxide interface in the JTE structure, rather than the trapping/detrapping at the SiC/gate oxide interface in the cell structure. A positive interface charge of approximately one-third of the sheet dopant concentration of the JTE region, lowers BV by 150 V, which is the typical measured BV slump of the DMOSFETs of this paper.     

Tunable Diode Laser Spectroscopy With Wavelength Modulation: A Phasor Decomposition Method for Calibration-Free Measurements of Gas Concentration and Pressure

The principles and implementation of a phasor decomposition method for analyzing signals in tunable diode laser spectroscopy with wavelength modulation are described. This new technique enables recovery of the isolated and normalized residual amplitude modulation (RAM) signal from measured first harmonic signals at any chosen fundamental modulation frequency. Like the previously reported RAM technique, this new approach is absolute, yielding gas absorption line shape functions, concentrations and pressures without the need for calibration, under certain defined operating conditions. It represents an advancement of the RAM technique in that it obviates the need to operate at a specific high frequency to achieve phase quadrature between the RAM and derivative signals: the signals may be recovered at their maximum levels at any frequency. Measurements of the 1650.96 nm and the 1666.2 nm rotation/vibration absorption line shape functions for 1% and 10% methane in nitrogen at various pressures are compared to theoretical predictions derived from HITRAN data. The excellent agreement confirms the validity of the new technique. Further measurements of concentration and pressure confirm the efficacy of the technique for determining concentration in industrial process environments where the pressure may be unknown and changing. With the above features this new method is particularly suited to stand alone instrumentation for on-line deployment in industrial processes where the calibration factors in the conventional approach would present significant difficulties.     

A Frequency Multiplication Resonant Inverter With Constant Frequency Phase Control

The schematic and analysis of a voltage-fed resonant inverter are presented in this paper. The topology of the inverter allows operation of the resonant tank at higher harmonics and multiples of the switching frequency. The resulting loss in voltage gain is compensated through the use of multiple commutation poles employing low-cost modestly rated MOSFETs. The proposed topology can control power throughput at a fixed frequency through pole phase-shift modulation. Zero voltage switching is maintained down to no load and within the entire input voltage range. Measurements from a multimegahertz 100-W inverter confirm the theoretical predictions, as well as the suggested design and control approach.     

Geographical variation of the conversion efficiency of crystalline silicon photovoltaic modules in Europe

We present a geographical assessment of the performance of crystalline silicon photovoltaic (PV) modules over Europe. We have developed a method that is based on a material specific analytical expression of the PV conversion efficiency, relative to nominal efficiency, as a function of module temperature and irradiance. This method is combined with a climate database that includes average daytime temperature and irradiance profiles. It is found that the geographical variation in ambient temperature and yearly irradiation causes a decrease in overall yearly PV performance from 3 to 13% relative to the performance under Standard Test Conditions, with the highest decrease found in the Mediterranean region. Based on the above results we developed a simplified linear expression of the relative PV module efficiency that is a simple function of yearly total irradiation and yearly average daytime temperature. The coefficients to the linear expression are found by fitting to the map resulting from the above‐mentioned analytical approach. The prediction of total yearly PV output from this linear fit deviates less than 0·5% from the more detailed calculation, thus providing a faster and more simplified alternative to the yield estimate, in the case when only limited climate data are available. Copyright © 2008 John Wiley & Sons, Ltd.     

A dual voltage-frequency VLSI chip for image watermarking in DCT domain

In this brief, we present a new VLSI architecture that can insert invisible or visible watermarks in images in the discrete cosine transform domain. The proposed architecture incorporates low-power techniques such as dual voltage, dual frequency, and clock gating to reduce the power consumption and exploits pipelining and parallelism extensively in order to achieve high performance. The supply voltage level and the operating frequency are chosen for each module so as to maintain the required bandwidth and throughput match among the different modules. A prototype VLSI chip was designed and verified using various Cadence and Synopsys tools based on TSMC 0.25-/spl mu/m technology with 1.4 M transistors and 0.3 mW of estimated dynamic power.     

On self-healing digital system design

In recent years there has been a significant growth of interest in exploiting the principles of biological processes to create powerful methodologies for solving computational problems. This paper discusses how these features have been exploited in digital hardware design. It also introduces an architecture for implementing self-healing digital systems that is inspired by the antigen protection mechanism employed by the human immune system. In the proposed architecture, a spare cell is dedicated to replace one in a group of four functional cells. Once one of these four functional cells is found to be faulty, the spare cell is cloned as the faulty cell. This architecture is especially suitable for tolerating soft errors in functional cells or on interconnect lines. Another major advantage of this architecture is that the outputs of functional cells are connected to the inputs of other physically adjacent functional cells, thus making it appropriate for nanocomputing system design.     

Architectural power analysis: The dual bit type method

This paper describes a novel strategy for generating accurate black-box models of datapath power consumption at the architecture level. This is achieved by recognizing that power consumption in digital circuits is affected by activity, as well as physical capacitance. Since existing strategies characterize modules for purely random inputs, they fail to account for the effect of signal statistics on switching activity. The dual bit type (DBT) model, however, accounts not only for the random activity of the least significant bits (LSB's), but also for the correlated activity of the most significant bits (MSB's), which contain two's-complement sign information. The resulting model is parameterizable in terms of complexity factors such as word length and can be applied to a wide variety of modules ranging from adders, shifters, and multipliers to register files and memories. Since the model operates at the register transfer level (RTL), it is orders of magnitude faster than gate- or circuit-level tools, but while other architecture-level techniques often err by 50-100% or more, the DBT method offers error rates on the order of 10-15%     

Truly temperature independent current conveyor precision rectifier

A current conveyor based rectifier circuit with very low temperature sensitivity is presented. The use of a current mirror arrangement to bias the rectifying diodes provides higher temperature stability than previously reported designs. The output offset voltage is easily adjustable to the desired optimum level