Bio-inspired delayed evolutionary game dynamics with?networking applications

We study in this paper some evolutionary games where competition between individuals from a large population occurs through many local interactions between randomly selected individuals. We focus on games that have the property of possessing a single interior evolutionarily stable strategy (ESS). We study in particular the effect of the time delays on the convergence of evolutionary dynamics to the ESS in an evolutionary game in which each pure strategy is associated with its own delay. In particular, we study a multiple access game as well as a Hawk and Dove game. We study the properties of the ESS in these games and also the effect of time delays on the convergence of various bio-inspired evolutionary game dynamics to the ESS.     

Sequential batch sampling

Let {X_i} be i.i.d.{F_θ}.We consider the testing problem H₁θ<θ₀ vs H₂θ≥θ₀, where sampling is done sequentially in batches with variable batch sizes.For some parametric families {F_θ}, and under natural cost struc-ture, we characterize the Bayes procedures. This characterization of Bayes procedures lead to a similar characterization of essentially complete class of procedures.     

Discriminatory processor sharing queues with stationary ergodic service times and the performance of TCP in overload

In a recent paper, Bonald and Roberts (2001) [6] studied non-persistent TCP connections in transient overload conditions, under the assumption that all connections have the same round-trip times. In this paper our goal is to develop theoretical tools that will enable us to relax this assumption and obtain explicit expressions for the rate of growth of the number of connections at the system, the rate at which TCP connections leave the system, as well as the time needed for the completion of a connection. To that end, we model the system as a discriminatory processor sharing (DPS) system which we analyze under very mild assumptions on the probability distributions related to different classes of arrivals: we only assume that the arrival rates of connections exist, and that the amount of information transmitted during a connection of a given type forms a stationary ergodic sequence. We then proceed to obtain explicit expressions for the growth rate of the number of connections at the DPS system for several specific probability distributions. We check through simulations the applicability of our queueing results for modeling TCP connections sharing a bottleneck.     

NROM: A novel localized trapping, 2-bit nonvolatile memory cell

This paper presents a novel flash memory cell based on localized charge trapping in a dielectric layer and on a new read operation. It is based on the storage of a nominal ~400 electrons above a n⁺/p junction. Programming is performed by channel hot electron injection and erase by tunneling enhanced hot hole injection. The new read methodology is very sensitive to the location of trapped charge above the source. This single device cell has a two physical bit storage capability. The cell shows improved erase performances, no over erase and erratic bit issues, very good retention at 250°C, and endurance up to 1M cycles. Only four masks are added to a standard CMOS process to implement a virtual ground array. In a typical 0.35 μm process, the area of a bit is 0.315 μm² and 0.188 μm² in 0.25 μm technology. All these features and the small cell size compared to any other flash cell make this device a very attractive solution for all NVM applications     

On the physical mechanism of the NROM memory erase

The purpose of this paper is to investigate the physical mechanism of NROM memory erase. Three conduction mechanisms potentially responsible of NROM erase will be analyzed (tunneling and emission of electrons through both bottom and top oxide, tunneling and injection of holes over the bottom oxide barrier) by means of standard two-dimensional simulations and ad-hoc models reproducing hole and electron transport mechanisms across the oxide not included in standard device simulators. Hot-hole injection will be identified as the actual conduction mechanism of NROM erase, and two compact models capable to describe the main characteristics of NROM erase current will be developed.     

On ACK filtering on a slow reverse channel

Acknowledgement (ACK) filtering has been proposed as a technique to alleviate the congestion at the input of a slow channel located on the reverse path of a TCP connection. Old ACKs waiting at the input of the slow channel are erased when new ACKs are to be queued. In the literature the case of one‐ACK per connection at a time has been studied. In this paper we show that this is too aggressive for short transfers where ACKs arrive in bursts due to the slow start phase, and where the TCP source needs to receive the maximum number of ACKs to increase fast its window. We study first static filtering where a certain ACK queue length is allowed. We show analytically how this length needs to be chosen. We present then some algorithms that adapt the filtering of ACKs as a function of the slow channel utilization rather than the ACK queue length. These algorithms provide a good compromise between reducing the ACK queueing delay and passing a large number of ACKs that guarantee a fast window increase. Copyright © 2003 John Wiley & Sons, Ltd.