Temperature compensated and gated CMOS ring oscillator for time-to-digital converter application

This paper presents a CMOS voltage controlled ring oscillator with temperature compensation for low power time-to-digital converters (TDCs). In order to maintain the oscillation frequency stable, a novel compensation circuit is proposed through adaptively sensing temperature variations. This design has been implemented in TSMC 0.35 μm CMOS standard process with an active area of under 0.039 mm². Experimental results show that the clock frequency is around 159.0 MHz only with a power consumption of 550 μA. As respective to the room temperature the maximum frequency variation is between ?3.46 and +3.08 % under temperature range of ?40 to 85 °C. The bit error time induced by clock jitter is limited within 4.8 % in the whole clock period, and the differential nonlinearity of the TDC is less than 0.408 LSB.     

An area-and-power-efficient 8.4-bit ENOB 30 MS/s SAR ADC in 65 nm CMOS

Area and power consumption are two main concerns for the electronics towards the digitalization of in-probe 3D ultrasound imaging systems. This work presents a 10-bit 30 MS/s successive approximation register analog-to-digital converter, which achieves good area efficiency as well as power efficiency, by using a symmetrical MSB-capacitor-split capacitor array with customized small-value finger capacitors. Moreover, simplified dynamic digital logic and a dynamic comparator have been designed. Fabricated in a 65 nm CMOS technology, the core circuit only occupies 0.016 mm². The ADC achieves a signal-to-noise ratio of 52.2 dB, and consumes 61.3 μW at 30 MS/s from a 1 V supply voltage, resulting in a figure of merit (FoM) of 6.2 fJ/conversion-step. The FoM defined by including the area is 0.1 mm² fJ/conversion-step.     

Switching scheme with 98.4% switching energy reduction and high accuracy for SAR ADCs

An energy-efficient digital-to-analogue converter (DAC) switching scheme with high-accuracy is proposed for successive approximation register (SAR) analogue-to-digital converters (ADCs). By utilizing a complementary switching method, the proposed switching scheme achieves a 98.4% switching energy reduction and a 75% area reduction compared to the conventional SAR ADC. Moreover, the accuracy of the SAR ADC is independent on the accuracy of the third reference voltage (V_cm) except the least significant bit, and the common-mode voltage of the DAC outputs keeps approximately unchanged during a conversion cycle, making the design of the SAR ADC more relaxed.     

Bio-cellular processes modeling on silicon substrate: receptor–ligand binding and Michaelis Menten reaction

Reducing transmit power is the most straightforward way towards more energy-efficient communications, but it results in lower SNRs at the receiver which can add a performance and/or complexity cost. At low SNRs, synchronization and channel estimation errors erode much of the gains achieved through powerful turbo and LDPC codes. Further expanding the turbo concept through an iterative receiver—which brings synchronization and equalization modules inside the loop—can help, but this solution is prohibitively complex and it is not clear what can and what cannot be a part of the iterative structure. This paper fills two important gaps in this field: (1) as compared to previous research which either focuses on a subset of the problem assuming perfect remaining parameters or is computationally too complex, we propose a proper partitioning of algorithm blocks in the iterative receiver for manageable delay and complexity, and (2) to the best of our knowledge, this is the first physical demonstration of an iterative receiver based on experimental radio hardware. We have found that for such a receiver to work, (1) iterative timing synchronization is impractical, iterative carrier synchronization can be avoided by using our proposed approach, while iterative channel estimation is essential, and (2) the SNR gains claimed in previous publications are validated in indoor channels. Finally, we propose a heuristic algorithm for simplifying the carrier phase synchronization in an iterative receiver such that computations of the log likelihood ratios of the parity bits can be avoided to strike a tradeoff between complexity and performance.     

Generation of square and triangular wave with independently controllable frequency and amplitude using OTAs only and its application in PWM

This paper presents a self-generating square/triangular wave generator using only the CMOS Operational Transconductance Amplifiers (OTAs) and a grounded capacitor. The output frequency and amplitude of the proposed circuit can be independently and electronically adjusted. The proposed circuit validates its advantage by consuming less amount of power, which is about 71.3 µW. The theoretical aspects are authentically showcased using the PSPICE simulation results. The performance of the proposed circuit is also verified through pre layout and post layout simulation results using the 90 nm GPDK CMOS parameters. A prototype of this circuit has been made using commercially available IC CA3080 for experimental verification. Experimentation also gives the similar output as per the theoretical proposition. The designed circuit is also made applicable to perform pulse width modulation (PWM).     

A Study of the Parasitic Properties of the Schottky Barrier Diode

In this paper, we present a newly designed parameter extraction method of the Schottky barrier diode (SBD) with the purpose of measuring and studying its parasitic properties. This method includes three kinds of auxiliary configurations and is named as three-configuration parameter extraction method (TPEM). TPEM has such features as simplicity of operation, self-consistence, and accuracy. With TPEM, the accurate parasitic parameters of the diode can be easily obtained. Taking a GaAs SBD as an example, the pad-to-pad capacitance is 7 fF, the air-bridge finger self-inductance 11 pH, the air-bridge finger self-resistance 0.6 Ω, and the finger-to-pad capacitance 2.1 fF. A more accurate approach to finding the value of the series resistant of the SBD is also proposed, and then a complete SBD model is built. The evaluation of the modeling technology, as well as TPEM, is implemented by comparing the simulated and measured I-V curves and the S-parameters. And good agreements are observed. By using TPEM, the influence of the variation of the geometric parameters is studied, and several ways to reduce the parasitic effect are presented. The results show that the width of the air-bridge finger and the length of the channel are the two largest influencing parameters, with the normalized impact factors 0.56 and 0.29, respectively. By using TPEM and the modeling technology presented in this paper, a design process of the SBD is proposed. As an example, a type of SBD suitable for 500–600 GHz zero-biased detection is designed, and the agreement between the simulated and measured results has been improved. SBDs for other applications could be designed in a similar way.     

Insights on the Side Panels of the <Emphasis Type="Italic">Franciscan Triptych</Emphasis> by Fra Angelico Using Terahertz Time-Domain Imaging (THz-TDI)

The side panels of the Franciscan Triptych (St. Jerome, St. John the Baptist, and the Archangel Gabriel and St. Francis, St. Onofrio, and the Virgin Annunciate, by Fra Angelico, before 1429) were scanned by means of terahertz time-domain imaging (THz-TDI). THz analysis supplied information on the stratigraphy of the panel paintings and the associated construction, “gessoing” and gilding techniques. Furthermore, THz-TDI provided information regarding the location of restoration materials within the painting stratigraphy on St. Jerome, St. John the Baptist, and the Archangel Gabriel, as well as on the extension and nature of subsurface cracks in the panel painting of St. Francis, St. Onofrio, and the Virgin Annunciate.     

A Reliability-Aware Methodology to Isolate Timing-Critical Paths under Aging

Temporal unreliability due to aging, such as Negative-Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) effects etc., in the CMOS circuits may not appear just after the chip production, instead it becomes apparent when it is used under certain workload and environmental conditions over time. Identifying aged paths that may become critical to circuit performance, is a real challenge for many researchers and reliability engineers. In this work, firstly we identify a set of parameters that impact the circuit performance under aging and use them in the proposed algorithm which is substantially faster than commercially available SPICE simulator with an approx 94% accuracy in estimating path delays. Secondly, we explore the possibility of using the proposed methodology, instead of using time expensive SPICE and pessimistic static timing analysis (STA), to identify a set of speed-limiting paths under aging. Experimental results demonstrate the effectiveness of the proposed algorithm and the associated methodology in comparison to SPICE simulated results.     

Machine learning based optimized live virtual machine migration over WAN links

Live virtual machine migration is one of the most promising features of data center virtualization technology. Numerous strategies have been proposed for live migration of virtual machines on local area networks. These strategies work perfectly in their respective domains with negligible downtime. However, these techniques are not suitable to handle live migration over wide area networks and results in significant downtime. In this paper we have proposed a Machine Learning based Downtime Optimization (MLDO) approach which is an adaptive live migration approach based on predictive mechanisms that reduces downtime during live migration over wide area networks for standard workloads. The main contribution of our work is to employ machine learning methods to reduce downtime. Machine learning methods are also used to introduce automated learning into the predictive model and adaptive threshold levels. We compare our proposed approach with existing strategies in terms of downtime observed during the migration process and have observed improvements in downtime of up to 15 %.     

Centralized dynamic frequency allocation for cell-edge demand satisfaction in fractional frequency reuse networks

Fractional frequency reuse (FFR) has emerged as a well-suited remedy for inter-cell interference reduction in the next-generation networks by allocating frequency reuse factor (FRF) of unity for the cell-center (CC) and higher FRF for the cell-edge (CE) users. However, this strict FFR comes at a cost of equal partitioning of frequency resources to the CE which most likely has varying demands in current networks. In order to mitigate this, we propose a centralized dynamic resource allocation scheme which allocates demand-dependent resources to CE users. The proposed scheme therefore outperforms the fixed allocation scheme of strict FFR for both CC and CE users. Complexity analysis provides a fair means of analyzing the suitability of proposed algorithm. We have also compared the proposed methodology with a reference dynamic fractional frequency reuse (DFFR) scheme. Results show maximum performance gain of up to 30% for 3 reference cells employing Rayleigh fading—through normalized area spectral efficiency (ASE) analysis for both fixed allocation and DFFR. Spectral efficiency analysis also indicates per-cell performance gain for both CC and CE users. Further, detailed three-dimensional ASE plots give insights into the affects to other cells. Due to dynamic nature of traffic loads, the proposed scheme is a candidate solution for satisfying the demands of individual cells.