Eliminating memory for fragmentation within partitionable SIMD/SPMDmachines

Efficient data layout is an important aspect of the compilation process. A model for the creation of perfect memory maps for large-scale parallel machines capable of user-controlled partitionable single-instruction-multiple data/single-program-multiple data (SIMD/SPMD) operation is developed. The term perfect implies that no memory fragmentation occurs and ensures that the memory map size is kept to a minimum. A major constraint on solving this problem is based on the single program nature of both the SIMD and SPMD modes of parallelism. It is assumed that all processors within the same submachine used identical addresses to access corresponding data items in each of their local memories. Necessary and sufficient conditions are derived for being able to create perfect memory maps, and results are applied to several partitionable interconnection networks     

Analysis of a stiffener intersection eccentricity in a steel containment

Containment structures have several regions in which the continuity of the cylindrical pressure boundary is interrupted, e.g., shell penetrations, discontinuous stiffeners, and changes in the shell thickness. Significant strain concentrations can occur in these areas of discontinuity. The Sandia National Laboratories 1:8-scale steel containment equipment hatch was analyzed as an example of an eccentricity at a stiffener intersection.A portion of the as-built 1:8-scale model was modeled with the ANSYS general purpose finite element program using triangular, thin shell finite elements. The overall size of the model was determined from Saint-Venant type considerations of the stress field around the hatch. Shell elements were used to model the ring and formed stiffeners. Geometric and material nonlinear behavior were included. The model was loaded using discrete load steps up to a pressure of 165 psig. At this pressure, the maximum strain was 19.7 percent in the formed stiffener near its intersection with the ring stiffener. The finite element solution demonstrated the very localized nature of the strain field near the ring/formed stiffener intersection.In an attempt to reduce analysis costs, a small portion of the 1:8-scale model immediately surrounding the ring/formed stiffener intersection was selected for further analysis. Two smaller models, a ring/formed stiffener intersection and a ring/circular stiffener intersection, were studied. The models were significantly smaller than the regions used previously. A comparison of the two intersection models showed that the circular stiffener is a more efficient configuration.     

Loss modeling and thermal measurement in planar inductors-a case study

This paper covers the experimental investigation and theoretical calculation of losses in a planar inductor under load. Finite-element software is used to perform the loss calculations. Thermally controlled experiments are performed for a range of frequencies to validate the corresponding finite-element method loss calculations. The thermal dependence of the loss mechanisms is also considered.     

New Reaction Engineering Concepts for Selective Oxidation Reactions

In order to enhance product yields in selective oxidation reactions, numerous reaction engineering concepts are being studied worldwide. Periodic operation has been investigated for decades, yet its application is limited to a few examples, such as the butane oxidation after DuPont or reverse-flow reactors for VOC removal. The use of microchannel reactors is a younger field, but it has already yielded promising results for process optimization. Catalytic wall reactors have proved to be a helpful tool for kinetic studies. On the laboratory scale, membrane reactors have displayed favorable behavior in selective oxidation. The Na vapor-catalyzed dehydrogenation of methanol to formaldehyde is a final example of an unusual new concept for selective oxidation.     

Modeling the Kinetics of Growth and the Properties of Nitrided Layers on Steels

Metal Science and Heat Treatment -     

A Symbolic Pole/Zero Extraction Methodology Based on Analysis of Circuit Time-Constants

This paper introduces a methodology for symbolic pole/zero extraction based on the formulation of the time-constant matrix of the circuits. This methodology incorporates approximation techniques specifically devoted to achieve an optimum trade-off between accuracy and complexity of the symbolic root expressions. The capability to efficiently handle even large circuits will be demonstrated through several practical circuits.