Oxidation of Starch by Hydrogen Peroxide in the Presence of UV Light-Part II

Various reaction variables in the hydrogen peroxide oxidation of starch in the presence of UV light have been investigated. Higher carboxyl and carbonyl contents of oxystarches were obtained under acidic than under alkaline conditions. Extent of oxidation was found to increase with time. Increasing the concentration of hydrogen peroxide results in an increase in the carboxyl and carbonyl contents. Apparently, air has no effect on the degree of oxidation whereas, oxygen seems to accelerate it.     

Teaching to Facilitate the Transfer of Learning [Educator's Corner]

An amusing anecdote that is old (having appeared in Esquire and Reader's Digest over half a century ago) concerns a man who experienced severe motion sickness during train travel whenever he would ride backwards, i.e., sat facing the rear of the train; so he learned to exchange such a seat by requesting the passenger sitting opposite to him. When he got off the train very sick and nauseated one day, his friend receiving him at the train station asked what was wrong. He replied that he had been riding the train backwards. Why didn't you ask the person sitting across from you to change seats with you? asked his friend. How could I, said the traveler, There wasn't anybody in that seat.     

Cylindrical gate all around Schottky barrier MOSFET with insulated shallow extensions at source/drain for removal of ambipolarity: a novel approach

In this paper TCAD-based simulation of a novel insulated shallow extension (ISE) cylindrical gate all around (CGAA) Schottky barrier (SB) MOSFET has been reported,to eliminate the suicidal ambipolar behavior (bias-dependent OFF state leakage current) of conventional SB-CGAA MOSFET by blocking the metal-induced gap states as well as unwanted charge sharing between source/channel and drain/channel regions.This novel structure offers low barrier height at the source and offers high ON-state current.The ION/IoFF of ISE-CGAA-SB-MOS-FET increases by 1177 times and offers steeper subthreshold slope (～60 mV/decade).However a little reduction in peak cut off frequency is observed and to further improve the cut-off frequency dual metal gate architecture has been employed and a comparative assessment of single metal gate,dual metal gate,single metal gate with ISE,and dual metal gate with ISE has been presented.The improved performance of Schottky barrier CGAA MOSFET by the incorporation of ISE makes it an attractive candidate for CMOS digital circuit design.The numerical simulation is performed using the ATLAS-3D device simulator.     

A QoS Aware Resource Placement Approach Inspired on the Behavior of the Social Spider Mating Strategy in the Cloud Environment

Wireless Personal Communications - The efficient management of resource sharing plays a crucial role in the cloud execution environment. The constraints such as heterogeneity and dynamic nature of...     

An analysis for AlGaN/GaN modulation doped field effect transistor using accurate velocity-field dependence for high power microwave frequency applications

An analytical model of Al_0.15Ga_0.85N/GaN modulation doped field effect transistor (MODFET), which uses an accurate velocity field relationship and incorporates the dominant effect of piezoelectric polarization induced charge at the AlGaN/GaN interface is presented. The effect of traps has also been taken into account. The calculated DC characteristics are in excellent agreement with the measured data. The model is extended to predict the microwave performance of the device. High current levels (>500 mA/mm), large transconductance (160.83 mS/mm) and a high cutoff frequency (9.6 GHz) have been achieved analytically and are in close agreement with the experimental data.     

A new grounded lamination gate (GLG) for diminished fringe-capacitance effects in high-/spl kappa/ gate-dielectric MOSFETs

A grounded lamination gate (GLG) structure for high-/spl kappa/ gate-dielectric MOSFETs is proposed, with grounded metal plates in the spacer oxide region. Two-dimensional device simulations performed on the new structure demonstrate a significant improvement with respect to the threshold voltage roll-off with increasing gate-dielectric constant (due to parasitic internal fringe capacitance), keeping the equivalent oxide thickness same. A simple fabrication procedure for the GLG MOSFET is also presented.     

Simulation study of Insulated Shallow Extension Silicon On Nothing (ISESON) MOSFET for high temperature applications

This paper analyzes the effect of temperature variation on various device architectures i.e. Insulated Shallow Extension Silicon On Nothing (ISESON), ISE and SON MOSFET using ATLAS 3D device simulator for 45 nm gate length. The simulation results obtained with the ATLAS has been validated by comparing it with reported experimental data of SON MOSFET. The simulation results demonstrate that out of three device designs, the ISESON MOSFET is the most suitable device for high speed, low voltage and high temperature applications. The integration of ISE and SON onto the conventional bulk MOSFET leads to the enhancement in analog device performance in terms of device efficiency (g_m/I_ds), device gain (g_m/g_d), output resistance (R_out) and early voltage (V_ea).