Neuro-Glia-Vascular-on-a-Chip System to Assess Aggravated Neurodegeneration via Brain Endothelial Cells upon Exposure to Diesel Exhaust Particles

Air pollution induces neurodegeneration, including cognitive deficits, neuroinflammation, and disruption of the blood–brain barrier. The mechanisms underlying air pollution-mediated neurodegeneration have not yet been fully elucidated given the limited knowledge on intercellular interactions. A brain-on-a-chip platform is presented comprising neurons, glia, and brain endothelial cells (bECs; neuro-glia-vascular, NGV) and diesel exhaust particle (DEP)-induced neurodegeneration is evaluated with a particular focus on the intercellular interactions. DEP exposure in the NGV model yields Alzheimer's disease-like signatures, including amyloid beta accumulation, tau phosphorylation, hydrogen peroxide (H₂O₂)/reactive oxygen species (ROS) production, and neuronal cell death. bEC-secreted granulocyte-macrophage colony-stimulating factor (GM-CSF) stimulates microglial activation and the overproduction of H₂O₂/ROS in microglia, suggesting that the bEC-microglia-neuron is a neurodegeneration cascade. Pharmacological inhibition at each step of the cascade, including GM-CSF neutralization, microglial activation suppression, and ROS scavenging, prohibits neurodegeneration in the NGV model. Therefore, intercellular interactions should be further studied of air pollution-induced neurodegeneration.     

A Low-Power Unified Arithmetic Unit for Programmable Handheld 3-D Graphics Systems

A low-power, area-efficient four-way 32-bit multifunction arithmetic unit has been developed for programmable shaders for handheld 3D graphics systems. It adopts the logarithmic number system (LNS) at the arithmetic core for the single-cycle throughput and the small-size low-power unification of various complicated arithmetic operations such as power, logarithm, trigonometric functions, vector-SIMD multiplication, division, square root and vector dot product. 24-region and 16-region piecewise linear logarithmic and antilogarithmic converters are proposed with 0.8% and 0.02% maximum conversion error, respectively. All the supported operations are implemented with less than 6.3% operation error and unified into a single arithmetic platform with maximum four-cycle latency and single-cycle throughput. A 93 K gate test chip is fabricated using one-poly five-metal 0.18-mum CMOS technology. It operates at 210 MHz with maximum power consumption of 15.3 mW at 1.8 V.     

Stretching‐Induced Growth of PEDOT‐Rich Cores: A New Mechanism for Strain‐Dependent Resistivity Change in PEDOT:PSS Films

It remains a fundamental challenge in the development of stretchable electronics to understand how mechanical strain changes the electrical properties of materials. Although the piezoresistive behavior of poly(3,4‐ethylene‐ dioxythiophene):poly(styrenesulfonate) (PEDOT:PSS) has been observed, its intrinsic origin is not yet fully understood because there are many extrinsic contributing factors and an experimental platform with which to assess such behavior has not been established. Here, systematic analysis shows that the matching Poisson's ratio and elastic modulus between PEDOT:PSS films and their underlying substrates is important in decoupling the factors that affect the material's piezoresistivity, allowing for tunable resistivity. Based on such a fundamental understanding, the conductivity of PEDOT:PSS can be controlled to be invariant and decrease as a function of applied tensile stress. Furthermore, a linear response of the resistivity with respect to mechanical strains of up to 60%, which has never before been realized, is shown. The irreversible conductivity enhancement is primarily caused by the coalescence‐induced growth of conductive PEDOT‐rich cores.     

A 400-mA current-mode buck converter with a self-trimming current sensing scheme

A current-programmed mode (CPM) controller is designed for improved DC–DC converter control. The key building block of the CPM controller is an accurate current-sensing circuit. This paper proposes a lossless current-sensing technique to measure the inductor current by measuring the current through the power transistor. A self-trimming circuit is used to compensate for any inaccuracies caused by voltage and temperature variations. The measurement results validate the operation of the fabricated chip.     

The impact of semiconductor technology scaling on CMOS RF and digital circuits for wireless application

The impact of CMOS technology scaling on the various radio frequency (RF) circuit components such as active, passive and digital circuits is presented. Firstly, the impact of technology scaling on the noise and linearity of the low-noise amplifier (LNA) is thoroughly analyzed. Then two new circuits, i.e., CMOS complementary parallel push-pull (CCPP) circuit and vertical-NPN (V-NPN) circuit for direct-conversion receiver (DCR), are introduced. In CCPP, the high RF performance of pMOS comparable to nMOS provides single ended differential RF signal processing capability without the use of a bulky balun. The use of parasitic V-NPN bipolar transistor, available in triple well CMOS technology, has shown to provide more than an order of magnitude improvement in 1/f noise and dc offset related problems, which have been the bottleneck for CMOS single chip integration. Then CMOS technology scaling for various passive device performances such as the inductor, varactor, MIM capacitor, and switched capacitor, is discussed. Both the forward scaling of the active devices and the inverse scaling of interconnection layer, i.e., more interconnection layers with effectively thicker total dielectric and metal layers, provide very favorable scenario for all passive devices. Finally, the impact of CMOS scaling on the various digital circuits is introduced, taking the digital modem blocks, the various digital calibration circuits, the switching RF power amplifier, and eventually the software defined radio, as examples.     

Study of efficient FEM-based iteration method for open regionproblem and its application to scattering from a three-dimensionalcavity-backed aperture

An efficient iterative finite element method for solving a three-dimensional scattering problem is proposed. With only a small number of meshes around a three-dimensional scatterer, the typical finite element method is shown to give an exact solution by carrying out several iterative updates of the radiation-type boundary conditions. The proposed method is used to analyse the scattering from a three-dimensional cavity-backed aperture, and the results obtained show good agreement with data obtained using another method     

Design and Analysis of Optimal Multi-Level Hierarchical Mobile IPv6 Networks

Hierarchical Mobile IPv6 (HMIPv6) is an enhanced version of Mobile IPv6 designed to reduce signaling overhead and to support seamless handoff in IP-based wireless/mobile networks. To support more scalable services, HMIPv6 networks can be organized as the form of a multi-level hierarchy architecture (i.e., tree structure). However, since multi-level HMIPv6 networks incur additional packet processing overhead at multiple mobility agents, it is important to find the optimal hierarchy level to minimize the total cost, which consists of the location update cost and the packet delivery cost. In this paper, we investigate this problem, namely the design of an optimal multi-level HMIPv6 (OM-HMIPv6) network. To accomplish this, we design a function to represent the location update cost and the packet delivery cost in multi-level HMIPv6 networks. Based on these formulated cost functions, we calculate the optimal hierarchy level in multi-level HMIPv6 networks, in order to minimize the total cost. In addition, we investigate the effects of the session-to-mobility ratio (SMR) on the total cost and the optimal hierarchy. The numerical results, which show various relationships among the network size, optimal hierarchy, and SMR, can be utilized to design an optimal HMIPv6 network. In addition, the analytical results are validated by comprehensive simulations. Sangheon Pack received his B.S. (2000, magna cum laude) and Ph.D. (2005) degrees from Seoul National University, both in computer engineering. He is a post doctor fellow in the School of Computer Science and Engineering at the Seoul National University, Korea. He is a member of the IEEE and ACM. During 2002–2005, he was a recipient of the Korea Foundation for Advanced Studies (KFAS) Computer Science and Information Technology Scholarship. He has been also a member of Samsung Frontier Membership (SFM) from 1999. He received a student travel grant award for the IFIP Personal Wireless Conference (PWC) 2003. He was a visiting researcher to Fraunhofer FOKUS, German in 2003. His research interests include mobility management, wireless multimedia transmission, and QoS provision issues in the next-generation wireless/mobile networks. Yanghee Choi received B.S. in electronics engineering from Seoul National University, M.S. in electrical engineering from Korea advanced Institute of Science, and Doctor of Engineering in Computer Science from Ecole Nationale Superieure des Telecommunications (ENST) in Paris, in 1975, 1977 and 1984 respectively. Before joining the School of Computer Engineering, Seoul National University in 1991, he has been with Electronics and Telecommunications Research Institute (ETRI) during 1977–1991, where he served as director of Data Communication Section, and Protocol Engineering Center. He was research student at Centre National d'Etude des Telecommunications (CNET), Issy-les-Moulineaux, during 1981–1984. He was also Visiting Scientist to IBM T.J. Watson Research Center for the year 1988–1989. He is now leading the Multimedia Communications Laboratory in Seoul National University. He is also director of Computer Network Research Center in Institute of Computer Technology (ICT). He was editor-in-chief of Korea Information Science Society journals. He was chairman of the Special Interest Group on Information Networking. He has been associate dean of research affairs at Seoul National University. He was president of Open Systems and Internet Association of Korea. His research interest lies in the field of multimedia systems and high-speed networking. Minji Nam received her B.S. and M.S degrees in Computer Science and Engineering from Seoul National University in 2003 and 2005, respectively. From 2005, she has worked on Portable Internet Development Team for Korea Telecom. Her research interests are mobile networks, portable internet technology (IEEE 802.16) and Mobile IPv6.     

A single capacitor loop filter phase-locked loop with frequency voltage converter

A novel phase-locked loop that has a loop filter consisting of only one capacitor is designed with a frequency voltage converter (FVC). Simulation and measurement results show that the proposed phase-locked loop (PLL) works stably demonstrating that the FVC works effectively as a resistor. Measurement results of the proposed PLL fabricated in a one-poly six-metal 0.18 μm CMOS process show that the phase noise is ?109 dBc/Hz at 10 MHz offset from 752.7 MHz output frequency.     

Architectural Design Issues in a Clockless 32‐Bit Processor Using an Asynchronous HDL

As technology evolves into the deep submicron level, synchronous circuit designs based on a single global clock have incurred problems in such areas as timing closure and power consumption. An asynchronous circuit design methodology is one of the strong candidates to solve such problems. To verify the feasibility and efficiency of a large‐scale asynchronous circuit, we design a fully clockless 32‐bit processor. We model the processor using an asynchronous HDL and synthesize it using a tool specialized for asynchronous circuits with a top‐down design approach. In this paper, two microarchitectures, basic and enhanced, are explored. The results from a pre‐layout simulation utilizing 0.13‐μm CMOS technology show that the performance and power consumption of the enhanced microarchitecture are respectively improved by 109% and 30% with respect to the basic architecture. Furthermore, the measured power efficiency is about 238 μW/MHz and is comparable to that of a synchronous counterpart.     

A low‐complexity single‐carrier frequency‐division multiple access transmitter

A framework for a computationally efficient single‐carrier frequency‐division multiple access (SC‐FDMA) transmitter is proposed in this paper. Compared with a wide system bandwidth, the uplink allocation for each user is supposed to be relatively small because of multiple user access, which makes each user's signal vector to be sparse. When the localized subcarrier allocation is used for SC‐FDMA, the inverse fast fourier transform can take advantage of the sparse user input vector to reduce its complexity. The analytical and simulation results show that the proposed framework can provide a significant complexity reduction compared with the conventional SC‐FDMA transmitter. Copyright © 2011 John Wiley & Sons, Ltd.