Power engineering industry interaction at Clemson University

The authors present a successful model of industry/university cooperation in establishing a strong power system curriculum in both the graduate and undergraduate level. Numerous long-term and short-term research projects have been developed to satisfy the university mission and to tackle challenging problems facing the power industry. A unique structure for the Clemson University Electric Power Research Association (CUEPRA) has been established to promote electric power system research and to meet the need for a working communication link between the power industry and the academic community. The power industries involvements in the power program at Clemson University and the strategic improvements that have been accomplished in research and education are outlined     

Development of improved methods for type testing present day mediumvoltage circuit breakers for outdoor service

Type testing for fault currents for medium-voltage circuit breakers rated at 15 kV to 72.5 kV is addressed. The ANSI designation of a new class of definite-purpose circuit breakers capable of switching transformer secondary faults and the introduction of the requirement for short-line-fault tests for breakers rated 72.5 kV and below have increased the difficulty of performing type tests in a testing laboratory. It is concluded that synthetic testing using the parallel current injection circuit is described in ANSI C37.081 provides the best available method for proving these complex requirements for medium-voltage circuit breakers     

A bidding decision index for construction contractors

Results from applying the model on a sample of contractors, the majority of whom were international and operating in Egypt, reinforces the credibility of the developed methodology, claim the authors.     

Dynamic programming implementation on array processor architectures

Dynamic Programming (DP) applies to many signal and image processing applications including boundary following, the Viterbi algorithm, dynamic time warping, etc. This paper presents an array processor implementation of generic dynamic programming. Our architecture is a SIMD array attached to a host computer. The processing element of the architecture is based on an ASIC design opting for maximum speed-up. By adopting a torus interconnection network, a dual buffer structure, and a multilevel pipeline, the performance of the DP chip is expected to reach the order of several GOPS. The paper discusses both the dedicated hardware design and the data flow control of the DP chip and the total array.This work was supported in part by the NATO, Scientific and Environmental Affairs Division, Collaborative Research Grant SA.5-2-05(CRG.960201)424/96/JARC-501.     

Potential-time measurements on mild steel in etch primer solutions

Experiments were carried out in a two pack system; polyvinyl butyral, zinc tetroxychromate in one pack, and phosphoric acid in the other with an isopropanol solvent in both packs. This study examines the functions of the phosphoric acid and the chromate containing pigment separately by utilising the feature that the alcohol dispersed components have sufficient conductivity to carry out potential-time measurements in the wet components before and during mixing.     

Design, manufacture and evaluation of a scalable high-performanceneural system

The authors describe a scalable neural system, HyperNet, based on a probabilistic RAM-based architecture and using a custom VLSI IC. A system using five HyperNet VLSI ICs and capable of realising up to 10240 neurons has been designed, manufactured and demonstrated to have the potential to learn more than three orders of magnitude faster than simulations on current workstations