Effect of pulse time gate on CsI(T1) light output

The mass and charge identification of secondary particles with Z < 4 by a large CsI(T1) scintillation detector is performed using pulse shape analysis and time-of-flight methods. The dependence of the light output on E, A and Z is studied in the energy range of 1–20 MeV/A and special attention is paid to the integration time of the photomultiplier anode signal. It is found that the behaviour of the calibration curves strongly depends on the choice of the integration time interval.     

Suppression control method for torque vibration of three-phase HB-type stepping motor utilizing feedforward control

This paper proposes a method to reduce the vibration of the three-phase HB-type stepping motor with cogging torque by the feedforward compensation control. The compensation signal to suppress the vibration of the motor frame is obtained by the repetitive controller installing an online Fourier transformer and utilizing an acceleration sensor attached to the motor frame or an acoustic sensor such as a microphone placed close to the frame. The sensor is used only for the acquisition of the feedforward compensation data. The feedforward compensation signal at an arbitrary operating point is derived from the amplitude and phase data of the frequency components and the operating point data. Compensation data obtained by the repetitive controller is applied to the operating point changed by reference frequency and load condition in steady state. The compensation signal for the new operating point will be generated from compensation data utilizing polynomial equation approximation and linear interpolation method. The effectiveness of this proposed method is confirmed by the experimental results.     

Hybrid ARQ scheme employing TCM and packet combining

A new hybrid automatic repeat request scheme employing packet combining based on the Viterbi decoder is presented. It is shown that the proposed form of combining, together with a rearrangement of the signal constellation, can outperform similar forms of packet combining such as average diversity combining     

Novel level-identifying circuit for flash multilevel memories

This paper presents a high-speed, small-area circuit specifically designed to identify the levels in the read out operation of a flash multilevel memory. The circuit is based on the analog computation of the Euclidean distance between the current read out from a memory cell and the reference currents that represent the different logic levels. An experimental version of the circuit has been integrated in a standard double-metal 0.7-μm CMOS process with a die area of only 140×100 μm². Operating under a 5-V power supply, this circuit identifies the read-out current of a memory cell, and associates it with the appropriate logic level in 9 ns     

Voiced speech excitation synthesis using a sinusoidal model

A modification to the `shape-invariant' sinusoidal speech model is proposed, whereby the phases of the component sinewaves used for the excitation are made to add coherently at each glottal closure. Applied to pitch and time-scale modification, higher quality synthetic speech is produced when large changes are required     

An expert aid to fault diagnosis and trouble-shooting in satellitecommunications

Presents the Satellite Communications Network Expert (SaNE), a knowledge-based aid designed to provide engineering support for fault diagnosis. The SaNE is composed of two elements: a satcom network model, which simulates the structure and functionality of a system based loosely upon a large military satcom network, and a diagnostic component, which uses knowledge- and model-based reasoning techniques to analyse system anomalies and diagnose possible causes for the alarms such networks generate. The development cycle is described, emphasising lessons learnt during development and testing and the advantages and disadvantages of the techniques applied. The goal of the SaNE project is primarily commercial acceptance rather than innovation. The authors illustrate how novel concepts can be implemented in a practical system without compromising this goal     

High-performance automatic target recognition through data-specificVLSI

Under the Mojave configurable computing project, we have developed a system for achieving high performance on an automatic target recognition (ATR) application through the use of configurable computing technology. The ATR system studied here involves real-time image acquisition from a synthetic aperture radar (SAR). SAR images exhibit statistical properties which can be used to improve system performance. In this paper, the Mojave configurable computing system uses field programmable gate arrays (FPGA's) to implement highly specialized circuits while retaining the flexibility of programmable components. A controller sequences through a set of specialized circuits in response to real-time events. Computer-aided design (CAD) tools have been developed to support the automatic generation of these specialized circuits. The resulting configurable computing system achieves a significant performance advantage over the existing solution, which is based on application specific integrated circuit (ASIC) technology