Microlens for efficient coupling between LED and optical fiber

A new fabrication method of a microlens is proposed that can be easily applied to optical devices and microlens systems. The proposed microlens is formed by self-surface tension and cohesion of UV curing material. Since the microlens is hardened by short time UV exposure, the fabrication process is very simple. Integration with surface emitting-light emitting diode (SE-LED) results in enhanced coupling to optical fiber with coupling efficiency larger than the conventional case by 1.5 times. We also made a hemispheric microlensed fiber using this method. Compared with a typical arc-lensed fiber and a flat-end fiber, the coupling efficiency is improved to 18% and 40%, respectively     

High-performance cell transistor design using metallic shieldembedded shallow trench isolation (MSE-STI) for Gbit generation DRAM's

In this paper, the cell transistor design issues for the Gbit level DRAM's with the isolation pitch of less than 0.2 μm caused by the inverse-narrow-channel effect (INCE) and the neighboring storage-node E-field penetration effect (NSPE) will be discussed. Then we propose novel DRAM cell transistor structure by employing metallic shield inside the shallow trench isolation (STI). As confirmed by three-dimensional (3-D) device simulation results, by suppressing the inverse narrow-channel effect and the neighboring storage-node E-field penetration effect using metallic shield inside STI, we can obtain reliable cell transistors with low-doped substrate, low junction leakage current and uniform V_TH a distribution regardless of the active width variation     

Low temperature annealing behaviors of the titanium films formed by the ionized sputtering process on (001) silicon substrates

We investigated the low temperature reactions between the Ti films created by the ionized sputtering process and the (001) single crystal silicon wafers using high resolution transmission electron microscopy and x-ray diffractometry. We observed that the amorphous Ti-Si intermixed layer is formed at the Ti-Si interface whose thickness increased with the thickness of the deposited Ti films. The amorphous interlayer grew upon annealing treatments at the temperatures below 450°C. We also observed that the crystallization of the amorphous interlayer occurred upon annealing at 500°C. The first formed phase is Ti₅Si₃ in contact with Ti films, which is epitaxial with Ti films. Upon further annealing at 500°C, the Ti₅Si₄ phase and C49 TiSi₂ phase formed in the regions close to Ti films and Si substrates, respectively.     

Performance characteristics of SOI DRAM for low-power application

Process integration of cell capacitors that can circumvent the usual difficulties of large topographic height difference and high-temperature process are presented. A 16 Mbit silicon-on-insulator (SOI) DRAM with a 0.3 μm design rule is successfully fabricated and analyzed for processing integrity and circuit performance based on process integration of the cell capacitor using the pattern-bonded SOI (PBSOI) technology. Measurements for the strobe access time (tRAC) acid the operation current (I_ccl) show significant improvement (over 25%) for the SOI DRAM compared to those for the 16 Mbit bulk counterpart with the same circuit and layout. On the transistor side, ultra-low-voltage transistor technology using the body bias control schemes is also implemented and investigated. Devices with small leakage current and almost ideal subthreshold swing are obtained. The results give us guidance for transistor and process schematics for low-voltage DRAM application     

Multichannel MLSE equalizer with parametric FIR channelidentification

We propose a parametric finite impulse response (FIR) channel identification algorithm, apply the algorithm to a multichannel maximum likelihood sequential estimation (MLSE) equalizer using multiple antennas, and investigate the improvement in the overall bit error rate (BER) performance. By exploring the structure of the specular multipath channels, we are able to reduce the number of channel parameters to provide a better channel estimate for the MLSE equalizer. The analytic BER lower bounds of the proposed algorithm as well as those of several other conventional MLSE algorithms in the specular multipath Rayleigh-fading channels are derived. In the derivation, we consider the channel mismatch caused by the additive Gaussian noise and the finite-length channel approximation error. A handy-to-use simplified BER lower bound is also derived. Simulation results that illustrate the BER performance of the proposed algorithm in the global system for mobile communications (GSM) system are presented and compared to the analytic lower bounds     

Clock multiplier using digital CMOS standard cells for high-speeddigital communication systems

The authors propose and evaluate the performance of a 2^N times clock multiplier that controls memory components for high-speed data communications. To improve the reliability of the circuit, a symmetric circuit structure is used, while to verify circuit operation by means of a simple method, an MVU estimator is found from simulation data. The proposed circuit can provide clock rates, which are usually required in the multiple phase shift keying (MPSK) or multiple quadrature amplitude modulation (MQAM) modulation schemes, of 2 to 2^N times that of the input clock     

A 16-bit carry-lookahead adder using reversible energy recoverylogic for ultra-low-energy systems

In this paper, we describe an energy-efficient carry-lookahead adder using reversible energy recovery logic (RERL), which is a new dual-rail reversible adiabatic logic. We also describe an eight-phase, clocked power generator that requires an off-chip inductor. For the energy-efficient design of reversible logic, we explain how to control the overhead of reversibility with a self-energy-recovery circuit. A test chip was implemented with a 0.8 μm CMOS technology, which included two 16-bit carry-lookahead adders to allow fair comparison: an RERL one and a static CMOS one. Experimental results showed that the RERL adder had substantial advantages in energy consumption over the static CMOS one at low operating frequencies. We also confirmed that we could minimize the energy consumption in the RERL circuit by reducing the operating frequency until adiabatic and leakage losses were equal     

Roles of sidewall oxidation in the devices with shallow trenchisolation

The effects of sidewall sacrificial and sidewall oxidations on the characteristics of devices with shallow trench isolation (STI) have been investigated. We found that sidewall sacrificial and sidewall oxidations significantly affected junction leakage and gate oxide integrity (GOI). The sidewall sacrificial oxidation was shown to reduce oxidation-induced stresses and make the trench top corner more rounded. This reduced stress and more rounded top corner led to much improved junction leakage and GOI. These results clearly show that the sidewall sacrificial oxidation is worth using, although it adds complexity to the STI process     

Improvement of P-channel SOI LDMOS transistor by adapting a newtapered oxide technique

On-resistance of P-channel REduced SURface Field (RESURF) lateral double-diffused MOS (LDMOS) transistors has been improved by using a new tapered TEOS field oxide on the drift region of the devices. The new tapered oxidation technique provides better uniformity, less than 3%, and reproducibility. With the similar breakdown voltage (V_B), at V_gs=-5.0 V, the specific on-resistance (R_sp) of the LDMOS with the tapered field oxide is about 31.5 mΩ·cm ², while that of the LDMOS with the conventional field oxide is about R_sp=57 mΩ·cm². The uniformities of R_sp and V_B are less than 5 and 3%, respectively     

Threshold voltage dependence of LOCOS-isolated thin-film SOINMOSFET on buried oxide thickness

Effects of buried oxide thickness on short-channel effect of LOCOS-isolated thin-film SOI n-MOSFETs have been investigated. Devices fabricated on SOI substrate with thin (100 nm) buried oxide have smaller roll-off of threshold voltage than those fabricated on SOI substrate with thick (400 nm) buried oxide. This is caused by a different boron concentration at the silicon film that results from the difference of stress with the buried oxide thickness. In the case of thin buried oxide, higher volumetric expansion of the field oxide causes higher stress at the interface between the silicon film and the surrounding oxide, including field and buried oxide, which prevents boron atoms from diffusing beyond the interface