An efficient implementation of SELF, a dynamically-typed object-oriented language based on prototypes

We have developed and implemented techniques that double the performance of dynamically-typed object-oriented languages. Our SELF implementation runs twice as fast as the fastest Smalltalk implementation, despite SELF's lack of classes and explicit variables.To compensate for the absence of classes, our system uses implementation-levelmaps to transparently group objects cloned from the same prototype, providing data type information and eliminating the apparent space overhead for prototype-based systems. To compensate for dynamic typing, user-defined control structures, and the lack of explicit variables, our system dynamically compilesmultiple versions of a source method, eachcustomized according to its receiver's map. Within each version the type of the receiver is fixed, and thus the compiler can statically bind andinline all messages sent toself.Message splitting andtype prediction extract and preserve even more static type information, allowing the compiler to inline many other messages. Inlining dramatically improves performance and eliminates the need to hard-wire low-level methods such as+, ==, andifTrue:.Despite inlining and other optimizations, our system still supports interactive programming environments. The system traverses internal dependency lists to invalidate all compiled methods affected by a programming change. The debugger reconstructs inlined stack frames from compiler-generated debugging information, making inlining invisible to the SELF programmer.This work has been generously supported by National Science Foundation Presidential Young Investigator Grant #CCR-8657631, and by IBM, Texas Instruments, NCR, Tandem Computers, Apple Computer, and Sun Microsystems.This paper was originally published inOOPSLA '89 Conference Proceedings (SIGPLAN Notices, 25, 10 (1989) 49–70).     

Bandwidth and region division for broadband multi-cell networks

A cell planning technique termed BRD (bandwidth and region division) is presented for overcoming interference, maintaining QoS (quality of service) and improving channel capacity over OFDM (orthogonal frequency division multiplexing)-based broadband cellular networks. Through an optimal combination of sectorization and zero padding, bandwidth and region division is achieved that minimizes the outage probability for forward-link cell planning. In order to verify the effectiveness of the proposed algorithm, a Monte Carlo simulation is performed over multi-cell environments.     

A practical approach for statistical matching of output queueing

We study a practical approach to match the performance of an output-queued switch statistically. For this purpose, we propose a novel switching architecture called a multiple input/output-queued (MIOQ) switch that requires no speedup for providing sufficient switching bandwidth. To operate an MIOQ switch in a practical manner, we also propose a multitoken-based arbiter which schedules the switch at a high operation rate and a virtual first-in first-out queueing scheme which guarantees the departure order of cells belonging to the same traffic flow at output. Additionally, we show that the proposed switch can naturally provide asymmetric bandwidth for inputs and outputs, which may be important in dealing with the links with different bandwidth demands. Finally, we compare the performance of an MIOQ switch with that of an output-queued switch and discuss the design criteria to match the performance of an output-queued switch.     

Data retention characteristics of sub-100 nm NAND flash memory cells

In contrast to the conventional theories, we have revealed that the most distinguished mechanism in the data retention phenomenon after Fowler-Nordheim (FN) stress in sub-100 nm NAND Flash memory cells is the annihilation of interface states. Interface state generation rate increases rapidly as the channel width of NAND flash cell decreases. Comparison of interface states and stress-induced leakage current (SILC) component during retention mode shows that the annihilation of interface states strongly affects data retention characteristics of the programmed cells.     

Orientation-based unique representation for planar curves and shapes

This paper presents an orientation-based representation for planar curves and shapes. The new representation can uniquely represent all types, of planar shapes, be it convex, nonconvex, polygonal, smoothly curved, or piecewise smooth shapes. It is based on a new parameterization, theabsolute integral orientation. This representation is invariant under translation and rotation. The absolute integral orientation is a parameter invariant under scaling. As a result, matching of similar shapes (i.e., determination of the relative orientation and the scaling factor) using the absolute integral orientation as the parameter is easier than using the arclength as the parameter. In addition, the new representation has the feature of adaptive sampling, making it more compact and efficient than arc-length-based representations.     

Obtaining shorter regular expressions from finite-state automata

We consider the use of state elimination to construct shorter regular expressions from finite-state automata (FAs). Although state elimination is an intuitive method for computing regular expressions from FAs, the resulting regular expressions are often very long and complicated. We examine the minimization of FAs to obtain shorter expressions first. Then, we introduce vertical chopping based on bridge states and horizontal chopping based on the structural properties of given FAs. We prove that we should not eliminate bridge states until we eliminate all non-bridge states to obtain shorter regular expressions. In addition, we suggest heuristics for state elimination that leads to shorter regular expressions based on vertical chopping and horizontal chopping.     

89-GHz fT room-temperature silicon MOSFETs

The authors report the implementation of deep-submicrometer Si MOSFETs that at room temperature have a unity-current-gain cutoff frequency (f_T) of 89 GHz, for a drain-to-source bias of 1.5 V, a gate-to-source bias of 1 V, a gate oxide thickness of 40 Å, and a channel length of 0.15 μm. The fabrication procedure is mostly conventional, except for the e-beam defined gates. The speed performance is achieved through an intrinsic transit time of only 1.8 ps across the active device region