Selective Data Deactivation Mechanism in Sustainable Area-based Cache for Mobile Social Networks

This paper presents a proposal of a more resilient mechanism of an area-based sustainable cache system under a temporary decrease of the number of terminals. This mechanism suppresses interruptions of data relay and disappearances of cache data in the cache continually. The core technology enables each terminal to retain the received data in cache areas as ??deactivated data?? instead of deleting the data, even after a terminal leaves the area. Deactivated data are not relayed outside the target designated cache area. The data are reactivated and redistributed to others as relay data once the terminal revisits there. Consequently, the data are shared across time. Furthermore, particularly addressing the limitation of terminal storage, we proposed an adaptive scheme to select which data should be retained as deactivation data. This new mechanism leverages the proposed method under the storage limitation. As presented at the end of this paper, the simulation evaluations underscore the effectiveness of the proposed mechanism, and the adaptive selective scheme of deactivated data.     

Contact-Barrier Free,High Mobility,Dual-Gated Junctionless Transistor Using Tellurium Nanowire

The gate-all-around nanowire transistor, due to its extremely tight electrostatic control and vertical integration capability, is a highly promising candidate for sub-5 nm technology nodes. In particular, the junctionless nanowire transistors are highly scalable with reduced variability due to avoidance of steep source/drain junction formation by ion implantation. Here a dual-gated junctionless nanowire p-type field effect transistor is demonstrated using tellurium nanowire as the channel. The dangling-bond-free surface due to the unique helical crystal structure of the nanowire, coupled with an integration of dangling-bond-free, high quality hBN gate dielectric, allows for a phonon-limited field effect hole mobility of 570 cm² V⁻¹ s⁻¹ at 270 K, which is well above state-of-the-art strained Si hole mobility. By lowering the temperature, the mobility increases to 1390 cm² V⁻¹ s⁻¹ and becomes primarily limited by Coulomb scattering. The combination of an electron affinity of ≈ 4 eV and a small bandgap of tellurium provides zero Schottky barrier height for hole injection at the metal-contact interface, which is remarkable for reduction of contact resistance in a highly scaled transistor. Exploiting these properties, coupled with the dual-gated operation, we achieve a high drive current of 216 μA μm⁻¹ while maintaining an on-off ratio in excess of 2 × 10⁴. The findings have intriguing prospects for alternate channel material based next-generation electronics.     

An Improved Thin Wire Representation for FDTD Computations

We have shown that finite-difference time-domain (FDTD) electromagnetic computations for a conductor system having a radius smaller than 0.15Deltar or larger than 0.65 Deltar (Deltar is the lateral side length of cells employed), modeled using arbitrary-radius-wire representations proposed so far with a time increment determined from the upper limit of Courant's stability condition, result in numerical instability. A primary factor causing this numerical instability is that the speed of waves propagating in the radial direction from the wire in the immediate vicinity of the wire exceeds the speed of light, and therefore, Courant's condition is not satisfied there. It is further shown that for these cases, the arbitrary-radius-wire representation can be improved by modifying the material parameters for the axial field components closest to the wire as well as those for the radial electric and circulating magnetic field components. The improved wire representation is effective in representing a wire whose radius ranges from 0.0001Deltar to 0.9Deltar.     

Growth energetics of Lactococcus lactis subsp. lactis biovar diacetylactis in cometabolism of citrate and glucose

Certain strains of lactic acid bacteria present in commercial cheese starters, characterized by faint transparent colonies on an agar plate containing 1 mg kg ⁻¹ crystal violet (CVT), were identified as Lactococcus lactis subsp. (ssp) lactis biovar diacetylactis. The effect of citrate on the growth of these strains (CVT strains) in the presence of glucose was studied, in comparison with L. lactis strains. Molar growth yield from glucose (Y_G, g dry weight/mole of glucose consumed) for CVT strains grown on glucose plus citrate was significantly higher than the control (i.e. without citrate), but not for other L. lactis strains tested. Enhanced Y_G was also observed at a pH-controlled experiment, indicating that enhanced Y_G did not result from a buffering effect of citrate. CVT strains, in contrast to other strains of the same species, were shown to obtain enough energy to enhance Y_G on glucose–citrate mixtures.     

A Reliable All-2D Materials Artificial Synapse for High Energy-Efficient Neuromorphic Computing

High-performance artificial synaptic devices are indispensable for developing neuromorphic computing systems with high energy efficiency. However, the reliability and variability issues of existing devices such as nonlinear and asymmetric weight update are the major hurdles in their practical applications for energy-efficient neuromorphic computing. Here, a two-terminal floating-gate memory (2TFGM) based artificial synapse built from all-2D van der Waals materials is reported. The 2TFGM synaptic device exhibits excellent linear and symmetric weight update characteristics with high reliability and tunability. In particular, the high linearity and symmetric synaptic weight realized by simple programming with identical pulses can eliminate the additional latency and power consumption caused by the peripheral circuit design and achieve an ultralow energy consumption for the synapses in the neural network implementation. A large number of states up to ≈3000, high switching speed of 40 ns and low energy consumption of 18 fJ for a single pulse have been demonstrated experimentally. A high classification accuracy up to 97.7% (close to the software baseline of 98%) has been achieved in the Modified National Institute of Standards and Technology (MNIST) simulations based on the experimental data. These results demonstrate the potential of all-2D 2TFGM for high-speed and low-power neuromorphic computing.     

Fabrication of carbon nanofibers using only ion beam irradiation to glassy carbon

Carbon nanofibers (CNFs) and carbon nanotubes (CNTs) are new carbon-based materials. However, the production of CNFs and CNTs is very difficult due to the complicated processes and high temperature involved. Therefore, a method of fabrication is required that enables high throughput at a low cost.Our previous study reported that oxygen ion beam energy of 500 eV applied to glassy carbon (GC) forms the finest pitch conical anti-reflection (AR) structures, and that an irradiation time of more than 24 min fabricates conical AR structures with heights of more than 250 nm. After the fabrication of the AR structures, irradiation by an argon ion (Ar⁺ beam changes the surface morphology, and oblique angle irradiation can form CNFs. Thus, we carried out oblique Ar⁺ beam irradiation on conical carbon protrusions on GC fabricated by oxygen ion beam irradiation. As a result, CNFs have been formed using oxygen and argon ion beam irradiation at room temperature. In addition, multi-wall CNT can be obtained by two-step ion beam irradiation.     

Two-tone metal pattern transfer technique using a single mold surface

There is growing demand for a fine metal-patterning technique to fabricate devices of the next generation, such as patterned media, plasmon photonics, and nanoscale electrodes. Nanotransfer printing (nTP) using a nanoscale patterned stamp has recently received considerable attention because of its high throughput and high resolution. To increase the throughput of the process further, it will be necessary to be able to use the stamp repeatedly, because fabrication of the stamp is a comparatively lengthy process. However, after the first transfer process, residual metal in the concave areas of the stamp obstructs the continuation of the transfer process. We examined a two-tone metal pattern transfer technique using a single mold after the first transfer process. The obstructive gold pattern in the mold could be removed and obtained as a negative tone by using a layer of polymer as a transfer substrate.     

Improved efficiency of polymer light-emitting diodes by inserting a hole transport layer formed without thermal treatment above glass transition temperature

We have demonstrated a significant improvement in the performance of polymer light-emitting diodes (PLEDs) by inserting the fluorene-triatylamine copolymer as hole transport layer (HTL) without a thermal treatment above the glass transition temperature (T_g). A thin HTL insolubilized by a thermal treatment above T_g is often inserted as an interlayer between an anode buffer layer and a light-emitting polymer (LEP) in PLEDs fabricated by using a conventional solution process. The evaporative spray deposition using ultradiluted solution (ESDUS) method has enabled fabricating polymer bilayer structure without an insolublizing procedure. The bilayer PLEDs fabricated by ESDUS without the thermal treatment showed significantly higher and more stable external quantum efficiency than PLEDs having the conventional interlayer. Thermal treatment above T_g of the copolymer would induce degradation of its hole injection property. Furthermore, ESDUS bilayer devices showed much higher power efficiency than interlayer devices when calcium was used for cathode. The improvements would be caused by the enhancement of hole injection and the effective electron blocking at the copolymer/LEP interface in the ESDUS bilayer devices.     

A highly integrated 40-MIPS (peak) 64-b RISC microprocessor

A 1-million transistor 64-b microprocessor has been fabricated using 0.8-μm double-metal CMOS technology. A 40-MIPS (million instructions per second) and 20-MFLOPS (million floating-point operations per second) peak performance at 40 MHz is realized by a self-clocked register file and two translation lookaside buffers (TLBs) with word-line transition detection circuits. The processor contains an integer unit based on the SPARC (scalable processor architecture) RISC (reduced instruction set computer) architecture, a floating-point unit (FPU) which executes IEEE-754 single- and double-precision floating-point operations a 6-KB three-way set-associative physical instruction cache, a 2-KB two-way set-associative physical data cache, a memory management unit that has two TLBs, and a bus control unit with an ECC (error-correcting code) circuit