The Measurement of Muscle Fiber Conduction Velocity Using a Gradient Threshold Zero-Crossing Method

The conduction velocity of myoelectric potential along muscle fiber is known to be an index of the degree of muscular fatigue or muscular disease. When detecting the myoelectric potential by means of surface electrodes, the conduction velocity must be extracted from an apparently random wave of a myoelectric signal. In this paper, a method for determining conduction velocity is proposed based upon a zero-crossing time delay measurement with reference to the derivative of a myoelectric signal. The slope value of the input signal provides an effective criterion for rejecting undesired zero crossing caused by noise. This method needs no spectral analysis nor correlation calculation. Compared to another previously reported zero-cossing approach using digital filter preprocessing, it shows a more accurate and rapid estimation of velocity.     

Monolithic integration of low-threshold-current 1.3 ?m GaInAsP/InP DFB lasers

Two 1.3 ?m GaInAsP/InP DFB lasers with low threshold currents (28 and 29 mA) were successfully integrated. Both DFB lasers operated continuously at temperatures of up to 68°C. The 12 ? separation in wavelength between the two lasers was produced by a 2 ? difference of the grating periods. A thermal interaction between the two lasers was estimated from the shift in their wavelengths.     

A 45-ns 64-Mb DRAM with a merged match-line test architecture

A single 3.3-V 64-Mb dynamic RAM (DRAM) with a chip size of 233.8 mm² has been fabricated using 0.4-μm CMOS technology with double-level metallization. The dual-cell-plate (DCP) cell structure is applied with a cell size of 1.7 μm², and 30-fF cell capacitance has been achieved using an oxynitride layer (t_eff=5 nm) as the gate insulator. The RAM implements a new data-line architecture called the merged match-line test (MMT) to achieve faster access time and shorter test time with the least chip-area penalty. The MMT architecture makes it possible to get a RAS access time of 45 ns and reduces test time by 1/16000. A parallel MMT technique, which is an extended mode of MMT, leads to the further test-time reduction of 1/64000. Therefore, all 64 Mb are tested in only 1024 cycles, and the test time is only 150 μs with 150-ns cycle time     

Extended selection of switching target faults in CONT algorithm for test generation

We describe an extended selection of switching target faults in the CONT algorithm. The main difficulty in test generation is the conflict that arises in the process of determining the signal values due to reconvergent fanouts. Conventional approaches for test generation change a signal value, which causes conflicts to another possible choice for backtracking. In the CONT algorithm, a strategy of switching target fault was proposed as a new backtracking mechanism. In this method, the target fault is switched to a new target fault instead of making an alternative assignment on the primary input value when a conflict occurs. A disadvantage of the CONT algorithm is that unjustified lines exist in the process of test generation. These unjustified lines make the procedure of switching targets complicated and restrict the possible choice in selecting the new target fault. In the new version of CONT, called CONT-2, we have removed the unjustified lines in the process of test generation and have extended to two target-fault types for switching targets. Implementing CONT-2 by a Fortran program, ISCAS85 benchmark circuits are examined. Experiments on a combined system with fault simulation followed by CONT-2 are also presented.     

Mixed body bias techniques with fixed V/sub t/ and I/sub ds/ generation circuits

There remains a need to improve sub-1-V CMOS VLSIs with respect to variation in transistor behavior. In this paper, to minimize variation in delay and the noise margin of the circuits in processors, we propose several mixed body bias techniques using body bias generation circuits. In these circuits, either the saturation region of the current between source and drain (I/sub ds/) or the threshold voltage (V/sub t/) of PMOS/NMOS is permanently fixed, regardless of temperature range or variation in process. A test chip that featured these body bias generation circuits was fabricated using a 130-nm CMOS process with a triple-well structure. The mixed body bias techniques which keep the I/sub ds/ of the MOS in the decoder and I/O circuits of a register file fixed and maintain the V/sub t/ of the MOS in both the memory cell and domino circuits of the register file fixed resulted in positive temperature dependence of delay from -40 /spl deg/C to 125 /spl deg/C, 85% reduction of the delay variation compared with normal body bias (NBB) at V/sub DD/ = 0.8 V. In addition, the results using these techniques show a 100-mV improvement in lower operating voltage compared with NBB at -40 /spl deg/C on a 4-kb SRAM.     

Ambipolar field-effect transistors with bilayered thiophene/phenylene co-oligomers

Bilayered organic field-effect transistors were fabricated by successive vapor-depositions of 1,4-bis{5-[4-(trifluoromethyl)phenyl]thiophene-2-yl}benzene (AC5-CF₃) and 5,5″-bis(4-biphenylyl)-2,2′:5′,2″-terthiophene (BP3T). With decreasing thickness of the n-type AC5-CF₃ film in contact with the dielectric layer, ambipolar characteristics were improved under both positive and negative gate biases. Two types of asymmetric source/drain electrodes were prepared by either obliquely shadowed lamination or mask-shifted depositions of AlLi and Au. The latter method in which the device was characterized without exposure to air after the electrode deposition of AlLi resulted in remarkable improvement of ambipolarity and reduction of leak currents. Finally, optimized ambipolar mobilities of μ_e = 5.00 × 10^?2 and μ_h = 1.56 × 10^?2 cm² V^?1 s^?1) were obtained with 5-nm-thick AC5-CF₃ and 30-nm-thick BP3T.     

Light-emitting field-effect transistors with π-conjugated liquid crystalline polymer driven by AC-gate voltages

Light-emitting field-effect transistors with a liquid crystalline polymer of poly[(9,9-dioctylfluorenyl-2,7-diyl)-co-bithiophene] (F8T2) were investigated under alternating current (AC) gate operations. Bottom-contact/top-gate devices were fabricated with indium-tin-oxide (ITO) source/drain electrodes, a poly(methyl methacrylate) dielectric and a gold gate electrode. The crystalline F8T2 film exhibited ambipolar characteristics with electron and hole mobilities of 1.8 × 10^?3 and 2.5 × 10^?3 cm²/V s, respectively, although the threshold voltage was considerably higher for electron injection. By applying square-wave voltages to the gate, light emission was obtained at the both edges of the source and drain electrodes by alternating injection of opposite carriers even when the source and drain were grounded. The light intensity was enhanced in the channel region by biasing the source negative while biasing the drain positive where the holes injected from the drain were transported to recombine with the electrons injected at the source edge.     

Effect of fabrication process on electrical properties of polymer/multi-wall carbon nanotube nanocomposites

Polymer/carbon nanotubes nanocomposites were fabricated by an in situ polymerization process using multi-wall carbon nanotubes (MWNT) as filler in an epoxy polymer. Effects of curing process, mixing speed, mixing time, addition of ethanol, timing of hardener addition, etc., in the fabrication process on the electrical properties of nanocomposites have been investigated. In the fabrication process, the effective formation of macroscopic conducting network in matrix is most important to enhance the electrical properties of nanocomposites. It was found that the curing temperature and the mixing conditions are key factors in the fabrication process, which influence the formation of conducting network significantly. Therefore, careful design of these factors in the fabrication process is required to achieve high electrical performances of nanocomposites. The experimental percolation threshold of the resultant nanocomposites was around 0.1 wt%. Moreover, a statistical percolation model was built up to numerically investigate the percolation threshold. The experimental electrical conductivity increases from the percolation threshold following a percolation-like power law with the identified critical exponent t as 1.75.     

Ab initio DFT study of ideal shear strength of polytypes of silicon carbide

Ab initio density functional calculations are performed to investigate the ideal shear deformation of SiC polytypes (3C, 2H, 4H, and 6H). The deformation of the cubic and the hexagonal polytypes in small strain region can be well represented by the elastic properties of component Si₄C-tetrahedrons. The stacking pattern in the polytypes affects strain localization, which is correlated with the generalized stacking fault energy profile of each shuffle-set plane, and the ideal shear strength. Compressive hydrostatic stress decreases the ideal shear strength, which is in contrast with the behavior of metals. __________ Translated from Problemy Prochnosti, No. 1, pp. 8–13, January–February, 2008.     

Measurement by multidirectional interferometers of the position and orientation of a positioning stage

A multidirectional interferometer system is developed to determine the position and orientation of a stage moved in a two-dimensional (2-D) space. In this system four corner-cube prisms are mounted on the moving stage, and four laser beams are incident on the corner cubes in different directions. Moving distances in the observed directions are measured by laser interferometers. The position and orientation of the stage are calculated from the moving distances of the corner cubes. Some experiments are done on the 2-D moving stage with four interferometers, and measurement errors are estimated from redundant data. The estimated accuracy is higher than 0.2 microm for translation and 0.3 x 10(-3) deg for rotation for a measurement range of 0.5 mm and 0.5 deg.