Characterizations and electrochemical performance of pure and metal-doped Li4Ti5O12 for anode materials of lithium-ion batteries

Pure and metal (Cu, Al, Sn, and V)-doped Li₄Ti₅O₁₂ powders are prepared with solid-state reaction method. The effects of dopants on the physical and electrochemical properties are characterized by using TGA, XRD, and SEM. Compared with pure Li₄Ti₅O₁₂, metal-doped Li₄Ti₅O₁₂ powders show structural stability and enhanced lithium ion diffusivity brought by doped metal ions. Voltage characteristics and initial charge–discharge characteristics according to the C rates in pure and metal-doped Li₄Ti₅O₁₂ electrode materials are studied. Pure Li₄Ti₅O₁₂ powder shows a relatively good discharge capacity of 164 mAh/g at a rate 0.2C, and some of metal-doped Li₄Ti₅O₁₂ powders show higher discharge capacities. Metal-doped Li₄Ti₅O₁₂ powders are promising candidates as anode materials for lithium-ion batteries.     

Electrospray preparation of hierarchically-structured mesoporous TiO₂ spheres for use in highly efficient dye-sensitized solar cells

We report a simple method to prepare hierarchically structured TiO(2) spheres (HS-TiO(2)), using an electrostatic spray technique, that are utilized for photoelectrodes of highly efficient dye-sensitized solar cells (DSSCs). This method has an advantage to remove the synthesis steps in conventional sol-gel method to form nano-sized spheres of TiO(2) nanoclusters. The fine dispersion of commercially available nanocrystalline TiO(2) particles (P25, Degussa) in EtOH without surfactants and additives is electro-sprayed directly onto a fluorine-dopoed tin-oxide (FTO) substrate for DSSC photoelectrodes. The DSSCs of HS-TiO(2) photoelectrodes show high energy conversion efficiency over 10% under illumination of light at 100 mW cm(-2), AM1.5 global. It is concluded from frequency-dependent measurements that the faster electron diffusion coefficient and longer lifetime of HS-TiO(2) than those in nonstructured TiO(2) contribute to the enhanced efficiency in DSSCs.     

Synchrotron X-ray reflectivity study of high dielectric constant alumina thin films prepared by atomic layer deposition

High dielectric constant (high-k) gate dielectric alumina films were prepared with nanoscale thicknesses on p-type silicon substrates by atomic layer deposition (ALD) with alternating pulses of trimethyl aluminum, nitrogen, ozone and nitrogen, and some of them were further thermally annealed. These high-k gate dielectric films were characterized by synchrotron X-ray reflectivity (XR), and the XR data were quantitatively analyzed, providing the following structural parameters of each gate dielectric film: the surface roughness and interfacial roughness, the electron density profile, the number of layers, and the thickness of individual layers. These structural characteristics were then analyzed in detail by considering the ALD processing conditions and post-thermal annealing history.     

A Reliable Multicast Routing Protocol Based on Recovery Points and FEC in Mobile Ad-hoc Networks

Multicasting is an essential service for mobile ad-hoc networks. A major challenge for multicasting in mobile ad-hoc networks (MANETs) is the unstable forwarding path. This work presents a reliable multicasting protocol for mobile ad-hoc networks. A virtual backbone is used as a shared structure for multiple sessions. A lost packet recovery scheme is developed for reliable packet transmission, called the Recovery Point (RP) scheme. The RP scheme maintains the data packets received from the source for recovering lost packets for its downstream RPs. In addition, we combine the Forward Error Correction (FEC) technology with our RP scheme to enhance the reliability of our RP scheme. A mergence scheme for RP is also proposed to avoid excessive control overhead. Our RP and FEC based scheme can be used to improve the reliability and efficiency of the traditional non-acknowledged multicasting approach. Experiments were conducted to evaluate the proposed multicasting scheme. The results demonstrate that our scheme outperforms other schemes in terms of packet delivery ratio and multicast efficiency. Furthermore, the simulation results also demonstrate that our approach is stable in networks with high mobility.

Excellent Switching Uniformity of Cu-Doped $hbox{MoO}_{x}/hbox{GdO}_{x}$ Bilayer for Nonvolatile Memory Applications

We have investigated a Cu-doped MoO_x/GdO_x bilayer film for nonvolatile memory applications. By adopting an ultrathin GdO_x layer, we obtained excellent device characteristics such as resistance ratio of three orders of magnitude, uniform distribution of set and reset voltages, switching endurance up to 10⁴ cycles, and ten years of data retention at 85degC. By adopting bilayer films of Cu-doped MoO_x/GdO_x, a local filament was formed by a two-step process. Improved memory characteristics can be explained by the formation of nanoscale local filament in the ultrathin GdO_x layer.     

Unified VLSI systolic array design for LZ data compression

Hardware implementation of data compression algorithms is receiving increasing attention due to exponentially expanding network traffic and digital data storage usage. In this paper, we propose several serial one-dimensional and parallel two-dimensional systolic-arrays for Lempel-Ziv data compression. A VLSI chip implementing our optimal linear array is fabricated and tested. The proposed array architecture is scalable. Also, multiple chips (linear arrays) can be connected in parallel to implement the parallel array structure and provide a proportional speedup     

Bendable and Splitter-Integrated Optical Subassembly Based on a Flexible Optical Board

A bendable and splitter-integrated optical subassembly (OSA) is suggested as a short-distance board-to-board optical interconnection. This OSA was fabricated by simply packaging a vertical-cavity surface-emitting laser on a flexible optical board having an embedded 1 $times$ 8 optical splitter waveguide. Finally, we measured various optical characteristics of the OSA, including insertion, twist, and bending losses.      

Effects of Interfacial Dielectric Layers on the Electrical Performance of Top‐Gate In‐Ga‐Zn‐Oxide Thin‐Film Transistors

We investigate the effects of interfacial dielectric layers (IDLs) on the electrical properties of top‐gate In‐Ga‐Zn‐oxide (IGZO) thin film transistors (TFTs) fabricated at low temperatures below 200°C, using a target composition of In:Ga:Zn = 2:1:2 (atomic ratio). Using four types of TFT structures combined with such dielectric materials as Si₃N₄ and Al₂O₃, the electrical properties are analyzed. After post‐annealing at 200°C for 1 hour in an O₂ ambient, the sub‐threshold swing is improved in all TFT types, which indicates a reduction of the interfacial trap sites. During negative‐bias stress tests on TFTs with a Si3N4 IDL, the degradation sources are closely related to unstable bond states, such as Si‐based broken bonds and hydrogen‐based bonds. From constant‐current stress tests of Id = 3 µA, an IGZO‐TFT with heat‐treated Si₃N₄ IDL shows a good stability performance, which is attributed to the compensation effect of the original charge‐injection and electron‐trapping behavior.     

Adaptive learning control of milling operations

An adaptive learning control of milling operations in order to improve productivity is presented. Basically, the proposed control system consists of two parts. A feedforward neural network is first developed to acquire the inverse-dynamics model of the controlled plant. Then, a fuzzy feedback mechanism is designed to perform an adaptive modification of connection weights for the feedforward neural network. Based on this control system, an on-line adjustment of feedrate to achieve a constant milling force under a variety of cutting conditions is shown.     

A leakage current mechanism caused by the interaction of residualoxidation stress and high-energy ion implantation impact in advancedCMOS technology

In this paper, we report abnormal junction leakage current characteristics in sub-quarter micron CMOS formed by OSELO-II isolation method and high-energy ion implantation for well formation. The phenomena have not been found in other isolation schemes such as single Si₃N₄ spacer OSELO (SSS-OSELO), modified conventional LOCOS (MLOCOS) and shallow trench isolation (STI). From the defect analysis and process simulation based on the actual recipe, the abnormal leakage is found to be generated from the lattice defects at the edge of field oxide and caused by the combination of oxidation stress, and high-energy ion implantation. A process condition in the high-energy ion implantation and isolation process is proposed to reduce the leakage current