Direct Transfer Printing with Metal Oxide Layers for Fabricating Flexible Nanowire Devices

A direct printing method for fabricating devices by using metal oxide transfer layers instead of conventional transfer media such as polydimethylsiloxane is presented. Metal oxides are not damaged by organic solvents; therefore, electrodes with gaps less than 2 μm can be defined on a metal oxide transfer layer through photolithography. In order to determine a suitable metal oxide for use as transfer layer, the surface energies of various metal oxides are measured, and Au layers deposited on these oxides are transferred onto polyvinylphenol (PVP). To verify the feasibility of our approach, Au source–drain electrodes on transfer layers and Si nanowires (NWs) addressed by the dielectrophoretic (DEP) alignment process are transferred onto rigid and flexible PVP‐coated substrates. Based on transfer test and DEP process, Al₂O₃ is determined to be the best transfer layer. Finally, Si NWs field effect transistors (FETs) are fabricated on a rigid Si substrate and a flexible polyimide film. As the channel length decreases from 3.442 to 1.767 μm, the mobility of FET on the Si substrate increases from 127.61 ± 37.64 to 181.60 ± 23.73 cm² V^?1 s^?1. Furthermore, the flexible Si NWs FETs fabricated through this process show enhanced electrical properties with an increasing number of bending cycles.     

Highly Power‐Efficient Rack‐Level DC Power Architecture Combined with Node‐Level DC UPS

This letter presents a highly efficient rack‐level DC power architecture combined with a node‐level DC uninterruptible power supply (UPS). The proposed system can provide almost the equivalent power efficiency of a high‐voltage DC data center without any change in the existing power infrastructure. The node‐level DC UPS combined with a power distribution board provides high power efficiency as well as lower UPS installation costs. Implemented on a rack, the entire power system can be monitored through a network.     

Sub‐Nanometer Level Size Tuning of a Monodisperse Nanoparticle Array Via Block Copolymer Lithography

The fabrication and catalytic application of a size‐tunable monodisperse nanoparticle array enabled by block copolymer lithography is demonstrated. Highly uniform vertical cylinder nanodomains are achieved in poly(styrene‐block‐4‐vinylpyridine) (PS‐b‐P4VP) diblock copolymer thin‐films by solvent annealing. The prominent diffusion of the anionic metal complexes into the protonated P4VP cylinder nanodomains occurs through specific electrostatic interactions in a weakly acidic aqueous solution. This well‐defined diffusion with nanoscale confinement enables preparation of the laterally ordered monodisperse nanoparticle array with sub‐nanometer level precise size tuning. The controlled growth of monodisperse nanoparticle arrays is proven by their catalytic use for vertical carbon nanotube (CNT) growth via plasma enhanced chemical vapor deposition (PECVD). Since the size of the catalyst particles is the decisive parameter for the diameters and wall‐numbers of CNTs, the highly selective growth of double‐walled or triple‐walled CNTs could be accomplished using monodisperse nanoparticle arrays.     

A Simple Space-Time-Frequency Block Code Scheme for Four Transmit Antennas

It is well known that the full rate and full diversity complex space-time block code (STBC) is not existed for four transmit antennas. In this letter, we propose a simple quasi-orthogonal space-time-frequency block code (QO-STFBC) scheme with four transmit antennas and n _R receive antennas, where every two transmit antennas constitute one group and each group transmits signals over different subcarriers. The receiver can separate the received signals from each group via odd/even index FFT operation. After recombining the separated received signals with received antennas, an equivalent half rate orthogonal STFBC (O-STFBC) can be used for decoding. Thus, the full rate and full diversity are achieved at the transmitter and receiver, respectively. Simulation result shows that the proposed QO-STFBC scheme has better performance than the other schemes, in rate 2 layered Alamouti scheme is about 4 dB, full rate QO-STBC scheme is about 5 dB and half rate O-STBC scheme is about 7 dB at 10^?3 BER for the transmission of 2 bits/s/Hz.     

Balanced RF Duplexer with Low Interference Using Hybrid BAW Resonators for LTE Application

A balanced RF duplexer with low interference in an extremely narrow bandgap is proposed. The Long‐Term Evolution band‐7 duplexer should be designed to prevent the co‐existence problem with the WiFi band, whose fractional bandgap corresponds to only 0.7%. By implementing a hybrid bulk acoustic wave (BAW) structure, the temperature coefficient of frequency (TCF) value of the duplexer is successfully reduced and the suppressed interference for the narrow bandgap is performed. To achieve an RF duplexer with balanced Rx output topology, we also propose a novel balanced BAW Rx topology and RF circuit block. The novel balanced Rx filter is designed with both lattice‐ and ladder‐type configurations to ensure excellent attenuation. The RF circuit block, which is located between the antenna and the Rx filter, is developed to simultaneously function as a balance‐to‐unbalance transformer and a phase shift network. The size of the fabricated duplexer is as small as 2.0 mm × 1.6 mm. The maximum insertion loss of the duplexer is as low as 2.4 dB in the Tx band, and the minimum attenuation in the WiFi band is as high as 36.8 dB. The TCF value is considerably lowered to ?16.9 ppm/°C.     

PbS and CdS Quantum Dot‐Sensitized Solid‐State Solar Cells: “Old Concepts,New Results”

Lead sulfide (PbS) and cadmium sulfide (CdS) quantum dots (QDs) are prepared over mesoporous TiO₂ films by a successive ionic layer adsorption and reaction (SILAR) process. These QDs are exploited as a sensitizer in solid‐state solar cells with 2,2′,7,7′‐tetrakis(N,N‐di‐p‐methoxyphenylamine)‐9,9′‐spirobifluorene (spiro‐OMeTAD) as a hole conductor. High‐resolution transmission electron microscopy (TEM) images reveal that PbS QDs of around 3 nm in size are distributed homogeneously over the TiO₂ surface and are well separated from each other if prepared under common SILAR deposition conditions. The pore size of the TiO₂ films and the deposition medium are found to be very critical in determining the overall performance of the solid‐state QD cells. By incorporating promising inorganic QDs (PbS) and an organic hole conductor spiro‐OMeTAD into the solid‐state cells, it is possible to attain an efficiency of over 1% for PbS‐sensitized solid‐state cells after some optimizations. The optimized deposition cycle of the SILAR process for PbS QDs has also been confirmed by transient spectroscopic studies on the hole generation of spiro‐OMeTAD. In addition, it is established that the PbS QD layer plays a role in mediating the interfacial recombination between the spiro‐OMeTAD⁺ cation and the TiO₂ conduction band electron, and that the lifetime of these species can change by around 2 orders of magnitude by varying the number of SILAR cycles used. When a near infrared (NIR)‐absorbing zinc carboxyphthalocyanine dye (TT1) is added on top of the PbS‐sensitized electrode to obtain a panchromatic response, two signals from each component are observed, which results in an improved efficiency. In particular, when a CdS‐sensitized electrode is first prepared, and then co‐sensitized with a squarine dye (SQ1), the resulting color change is clearly an addition of each component and the overall efficiencies are also added in a more synergistic way than those in PbS/TT1‐modified cells because of favorable charge‐transfer energetics.     

Application of Plasma-Doping (PLAD) Technique to Reduce Dark Current of CMOS Image Sensors

Plasma doping (PLAD) was applied to reduce the dark current of CMOS image sensor (CIS), for the first time. PLAD was employed around shallow trench isolation (STI) to screen the defective sidewalls and edges of STI from the depletion region of photodiode. This technique can provide not only shallow but also conformal doping around the STI, making it a suitable doping technique for pinning purposes for CISs with sub-2-mum pixel pitch. The measured results show that temporal noise and dark signal deviation as well as dark level decrease     

A fully differential LC-VCO using a new varactor control structure

This paper presents a fully differential inductor-capacitor voltage-controlled oscillator (LC-VCO) with a new differentially-tuned varactor structure. The proposed LC-VCO has lower phase noise and better robustness to the injected common-mode noise than the differentially-tuned LC-VCO using the previous antiparallel structure. The LC-VCO implemented using 0.5-/spl mu/m SiGe BiCMOS technology is tunable from 4.251 to 4.428 GHz and the measured phase noise is -119 dBc/Hz at 1-MHz offset over the entire tuning range. Its core current is only 1.7 mA at 2.5-V supply voltage.     

Laser Process Proximity Correction for Improvement of Critical Dimension Linearity on a Photomask

We report on the improvement of critical dimension (CD) linearity on a photomask by applying the concept of process proximity correction to a laser lithographic process used for the fabrication of photomasks. Rule‐based laser process proximity correction (LPC) was performed using an automated optical proximity correction tool and we obtained dramatic improvement of CD linearity on a photomask. A study on model‐based LPC was executed using a two‐Gaussian kernel function and we extracted model parameters for the laser lithographic process by fitting the model‐predicted CD linearity data with measured ones. Model‐predicted bias values of isolated space (I/S), arrayed contact (A/C) and isolated contact (I/C) were in good agreement with those obtained by the nonlinear curve‐fitting method used for the rule‐based LPC.