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21.
In this paper, we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high-performance cache memories using single V/sub t/ (transistor threshold voltage) process. We utilize the concept of gated-ground (nMOS transistor inserted between ground line and SRAM cell) to achieve a reduction in leakage energy without significantly affecting performance. Experimental results on gated-ground caches show that data is retained (DRG-Cache) even if the memory is put in the standby mode of operation. Data is restored when the gated-ground transistor is turned on. Turning off the gated-ground transistor in turn gives a large reduction in leakage power. This technique requires no extra circuitry; the row decoder itself can be used to control the gated-ground transistor. The technique is applicable to data and instruction caches as well as different levels of cache hierarchy, such as the L1, L2, or L3 caches. We fabricated a test chip in TSMC 0.25-/spl mu/m technology to show the data retention capability and the cell stability of the DRG-Cache. Our simulation results on 100-nm and 70-nm processes (Berkeley Predictive Technology Model) show 16.5% and 27% reduction in consumed energy in L1 cache and 50% and 47% reduction in L2 cache, respectively, with less than 5% impact on execution time and within 4% increase in area overhead. 相似文献
22.
Kim C.H. Jae-Joon Kim Ik-Joon Chang Roy K. 《Solid-State Circuits, IEEE Journal of》2006,41(1):170-178
Effectiveness of previous SRAM leakage reduction techniques vary significantly as the leakage variation gets worse with process and temperature fluctuation. This paper proposes a simple circuit technique that adaptively trades off overhead energy for maximum leakage savings under severe leakage variations. The proposed run-time leakage reduction technique for on-die SRAM caches considers architectural access behavior to determine how often the SRAM blocks should enter a sleep mode. A self-decay circuit generates a periodic sleep pulse with an adaptive pulse period, which puts the SRAM array into a sleep mode more frequently at high leakage conditions (fast process, high temperature) and vice versa. An 0.18-/spl mu/m 1.8-V 16-kbyte SRAM testchip shows 94.2% reduction in SRAM cell leakage at a performance penalty less than 2%. Measurement results also indicate that our proposed memory cell improves SRAM static noise margin by 25%. 相似文献
23.
You-Chang Ko Roy S. Choong-Ho Cho Hyong-Woo Lee Garg H.K. 《Communications Letters, IEEE》2009,13(9):640-642
This letter introduces a new tree-based anti-collision scheme using multiple feedbacks for uplink tag random access in a single-cell scenario. We examine MAC efficiency improvements that result from the proposed scheme in terms of uplink (UL) throughput for emerging radio frequency identification (RFID) networks, and compare it with the conventional tree based RFID MAC in ISO 18000-6 Type B standard. 相似文献
24.
This paper describes the efforts of the Indian government to upgrade its power system to account for the increasing interconnections due to rapid regional development. These include the unibus act (EA2003), which addresses the issue of public sector monopoly and opens up the field for competition, private participation and reforms, and the implementation of the ABT to the intrastate level. The reforms and restructuring policies of the government have assured an adequate rate of return to investors. The national electricity policy implementation is expected to fulfill the aim of meeting more demand at a higher security level. 相似文献
25.
Graded gate oxide process involves a two-step synthesis of growing an oxide at a temperature above the viscoelastic temperature (TVE ) onto a pregrown low temperature thermally grown SiO2 layer to form a composite graded SiO2 structure. The cooling rate is carefully modulated near TVE~925°C to enhance growth induced stress relaxation. The pregrown SiO2 layer provides grading and is a sink for stress accommodation for the final high temperature SiO2 forming the interface. Both grading and modulated cooling generate a strain-free and planar Si/SiO2 interface. Such an interface delivers significant enhancement in all aspects of device reliability and performance. These oxides are of very high-quality, robust, and manufacturable with a process capability index, Cpk>1.5. Graded gate oxide is already in the primary path of our 0.16 μm and 0.12 μm technologies 相似文献
26.
Md A Hamid Sachchidananda D Chowdhury Md A Razzak Chitta R Roy 《Journal of the science of food and agriculture》1993,61(1):137-139
Growing ducklings were fed diets containing an aquatic weed Lemna trisulaca meal (LTM) replacing, on a protein basis, either 40, 60 or 80 g kg?1 of the fish meal (FM) from a control diet which contained 120 g FM kg?1. Partial replacement of FM (40 and 60 g kg?1 of the FM) by LTM on a protein basis showed good growth and low food consumption but food conversion efficiency was found to be comparable. It was concluded that LTM could be considered as a protein feed supplement for growing ducklings and also as a part replacement of animal protein (FM) in the nutrition of growing ducklings without deleterious effect on performance. 相似文献
27.
Channel coding for an impulse noise environment modeled as a Cauchy-Gaussian mixture is addressed. Code design based on the pairwise probability of error indicates the suitability of Hamming distance as a primary determinant of performance. Simulation results of code performance for the maximum likelihood (ML) and several suboptimal metrics are presented 相似文献
28.
Cutoff rates for (perfect) coordinate interleaving over flat Rayleigh fading channels are computed for some representative two-dimensional (2-D) and four-dimensional (4-D) quadrature amplitude modulation (QAM) schemes and compared to the standard symbol interleaved approaches. It is shown that for optimized coordinate interleaving [i.e., using optimum rotation parameters that maximize the cutoff rate for a given signal-to-noise ratio (SNR)], coding gains can be achieved vis-a-vis symbol interleaving that increases with the dimensionality of the signal constellation. Perfect coherent detection, as well as perfect channel state information are assumed 相似文献
29.
Mansoor Alam Tarasankar DebRoy Rustum Roy 《Journal of the American Ceramic Society》1990,73(3):733-735
High-pressure phases of CaCO3 , namely aragonite, calcite II, and possibly calcite III, were synthesized in air by exposing 10- to 20-μm-size particles of CaCO3 (calcite I phase) to a CO2 laser radiation at short pulse lengths (≤0.1 ms). The process, therefore, has the same effect as exposing the particles to at least several hundred megapascals pressure. Processing at higher pulse lengths resulted in the decomposition of CaCO3 to CaO and CO2 . The extent of decomposition increased with increasing pulse length. 相似文献
30.
This paper presents a technique for generating numerically an incident tapered beam of a prescribed polarization and a prescribed incidence angle by summing a finite number of propagating uniform plane waves, each constituent plane wave having its own magnitude, phase, incidence angle and polarization. Our three ad-hoc schemes for choosing the magnitude, the incidence angle and the polarization of a constituent plane wave are different from those by Braunisch et al. Our choice of the propagating plane waves corresponds to a sampling of the physical angular (/spl theta/, /spl phi/) space. This contrasts with the two-dimensional Fourier transform technique by Braunisch et al. and its Cartesian sampling of the (k/sub x/, k/sub y/) spectral plane where k/sub x/=(k/sub o/sin/spl theta/cos/spl phi/) and k/sub y/=(k/sub o/sin/spl theta/sin/spl phi/). Our technique is based on the summation of only propagating plane waves, whereas the technique by Braunisch et al. is based on the summation of both propagating and evanescent plane waves. 相似文献