Updating a steel mill power system to improve reliability anddecrease energy costs

The cost of electricity and operating reliability in heavy industry can be key in determining which processes and plants survive in today's competitive market. This paper provides an insight into the planning and implementation of several significant cost saving and reliability improvements at a turn-of-the-century steel mill in Ohio. A clear understanding of what to look for and how to proceed with such projects should provide motivation for others considering similar improvements     

Simultaneous design of power stage and controller for switchingpower supplies

This paper develops a method for simultaneously designing the power stage and controller for a switching power supply. The method utilizes a numerical optimization procedure, which facilitates computer-aided design. It is found that better performance can be achieved than with a traditional two-step design process, where the power stage and controller are designed sequentially. Optimization and simulation results for a buck power converter are presented to illustrate the design process and benefits     

Charge comparison protection of transmission lines-relayingconcepts

The authors describe the relaying concepts of charge comparison. Charge comparison is a new transmission line protection system. It is a form of current differential relaying. Charge comparison largely resolves the traditional problems of current differential relaying of transmission lines, which are that protection is lost if a channel fails, a large channel capacity is required, and precise channel delay compensation is required. This technique is suitable for the protection of two- or three-terminal AC transmission lines, of all lengths and voltage levels, with or without series of shunt compensation, with three-hole or single-pole tripping     

Synthesis and release of ATP by soluble mitochondrial F1 in complex with its inhibitor protein during dimethylsulfoxide-water transitions

Soluble mitochondrial F1 and F1 in complex with the natural ATPase inhibitor protein (F1-IP) catalyze the spontaneous synthesis of [gamma-32P]ATP from medium [32P]phosphate and enzyme-bound ADP when incubated in media with dimethylsulfoxide (Me2SO); under these conditions, the synthesized [gamma-32P]ATP is not released into the media, it remains tightly bound to the enzymes [Gómez-Puyou, A., Tuena de Gómez-Puyou, M. & de Meis, L. (1986) Eur. J. Biochem. 159, 133-140]. Some of the characteristics of the synthesized [gamma-32P]ATP were studied in F1 and F1-IP (ATPase activities of 70 and 1-3 micromol x min(-1) x mg(-1), respectively). In Me2SO media, gamma-phosphate of synthesized ATP in F1 or F1-IP exchanges with medium phosphate. From the rates of the exchange reaction, the half-times for hydrolysis of the synthesized ATP in F1 and F1-IP were calculated: 45 min and 58 min for F1 and F1-IP, respectively. The course that synthesized [gamma-32P]ATP follows after dilution of the Me2SO synthetic mixture with aqueous buffer was determined. After dilution, the half-life of synthesized ATP in F1 was less than 1 min. In F1-IP, ATP was also hydrolyzed, but at significantly lower rates. In F1-IP, dilution also produced release of the synthesized [gamma-32P]ATP. This was assayed by the accessibility of [gamma-32P]ATP to hexokinase. About 25% of [gamma-32P]ATP synthesized in F1-IP, but not in F1, was released into the media after dilution with aqueous buffer that contained 20 mM phosphate. Release of tightly bound ATP required the binding energy of phosphate and solvation of F1-IP, however, the particular kinetics of F1-IP were also central for medium ATP synthesis in the absence of electrochemical H+ gradients.     

Identification and disruption of a plant shaker-like outward channel involved in K+ release into the xylem sap

SKOR, a K+ channel identified in Arabidopsis, displays the typical hydrophobic core of the Shaker channel superfamily, a cyclic nucleotide-binding domain, and an ankyrin domain. Expression in Xenopus oocytes identified SKOR as the first member of the Shaker family in plants to be endowed with outwardly rectifying properties. SKOR expression is localized in root stelar tissues. A knockout mutant shows both lower shoot K+ content and lower xylem sap K+ concentration, indicating that SKOR is involved in K+ release into the xylem sap toward the shoots. SKOR expression is strongly inhibited by the stress phytohormone abscisic acid, supporting the hypothesis that control of K+ translocation toward the shoots is part of the plant response to water stress.     

Performance of interface engineeredSiNx/ICL/InP/In0.53Ga0.47As/InP dopedchannel HIGFET's

SiN_x/InP/InGaAs doped channel passivated heterojunction insulated gate field effect transistors (HIGFETs) have been fabricated for the first time using an improved In-S interface control layer (ICL). The insulated gate HIGFETs exhibit very low gate leakage (10 nA@V_GS =±5 V) and I_DS (sat) of 250 mA/mm. The doped channel improves the DC characteristics and the HIGFETs show transconductance of 140-150 mS/mm (L_g=2 μm), f_t of 5-6 GHz (L_g=3 μm), and power gain of 14.2 dB at 3 GHz. The ICL HIGFET technology is promising for high frequency applications     

Threshold voltage-minimum gate length trade-off in buried channelPMOS devices for scaled supply voltage CMOS technologies

The trade-off between threshold voltage (V_th) and the minimum gate length (L_min) is discussed for optimizing the performance of buried channel PMOS transistors for low voltage/low power high-speed digital CMOS circuits. In a low supply voltage CMOS technology it is desirable to scale V_th and L_min for improved circuit performance. However, these two parameters cannot be scaled independently due to the channel punch-through effect. Statistical process/device modeling, split lot experiments, circuit simulations, and measurements are performed to optimize the PMOS transistor current drive and CMOS circuit speed. We show that trading PMOS transistor V_th for a smaller L_min results in faster circuits for low supply voltage (3.3 to 1.8 V) n⁺-polysilicon gate CMOS technology, Circuit simulation and measurements are performed in this study. Approximate empirical expressions are given for the optimum buried channel PMOS transistor V _th for minimizing CMOS circuit speed for cases involving: (1) constant capacitive load and (2) load capacitance proportional to MOS gate capacitance. The results of the numerical exercise are applied to the centering of device parameters of a 0.5 μm 3.3 V CMOS technology that (a) matches the speed of our 0.5 μm 5 V CMOS technology, and (b) achieves good performance down to 1.8 V power supply. For this process the optimum PMOS transistor V_th (absolute value) is approximately 0.85-0.90 V