Multi-heterojunction large area HgCdTe long wavelength infrared photovoltaic detector for operation at near room temperatures

This paper describes a new multi-heterojunction n ⁺pp photovoltaic infrared photodetector. The device has been developed specifically for operation at temperatures of 200–300K in the long wavelength (8–14 μm) range of the infrared spectrum. The new structure solves the perennial problems of poor quantum efficiency and low dynamic resistance found in conventional long wavelength infrared photovoltaic detectors when operated near room temperature. Computer simulations show that devices with properly optimized multiple heterojunctions are capable of achieving the performance limits imposed by the statistical nature of thermal generation-recombination processes. In order to demonstrate the technology, multiple heterojunction devices have been fabricated on epilayers grown by isothermal vapor phase epitaxy of HgCdTe and in situ As p-type doping. The detector structures were formed using a combination of conventional dry etching, angled ion milling, and angled thermal evaporation for contact metal deposition. These multi-junction n ⁺pp HgCdTe heterostructure devices exhibit performances which make them useful for many applications. D* of optically immersed multiple heterostructure photovoltaic detectors exceeding 10⁸cmHz^1/2/W were measured at λ=10.6 μm and T=300K.     

Computationally effective algorithm for robust weighted averaging

One of the greatest disadvantages of the weighted signal averaging method is its sensitivity to the presence of noise and outliers in data and the need to estimate the noise variance in all signal cycles. The robust weighted averaging method based on the epsilon-insensitive loss function is free of these disadvantages, but has a very high computational burden and requires a choice of the insensitivity parameter epsilon. In this study, a new computationally effective algorithm for robust weighted averaging with automatic adjustment of the insensitivity parameter is introduced.     

Likelihood based hierarchical clustering

This paper develops a new method for hierarchical clustering. Unlike other existing clustering schemes, our method is based on a generative, tree-structured model that represents relationships between the objects to be clustered, rather than directly modeling properties of objects themselves. In certain problems, this generative model naturally captures the physical mechanisms responsible for relationships among objects, for example, in certain evolutionary tree problems in genetics and communication network topology identification. The paper examines the networking problem in some detail to illustrate the new clustering method. More broadly, the generative model may not reflect actual physical mechanisms, but it nonetheless provides a means for dealing with errors in the similarity matrix, simultaneously promoting two desirable features in clustering: intraclass similarity and interclass dissimilarity.     

Internet tomography

Today's Internet is a massive, distributed network which continues to explode in size as e-commerce and related activities grow. The heterogeneous and largely unregulated structure of the Internet renders tasks such as dynamic routing, optimized service provision, service-level verification, and detection of anomalous/malicious behavior increasingly challenging tasks. The problem is compounded by the fact that one cannot rely on the cooperation of individual servers and routers to aid in the collection of network traffic measurements vital for these tasks. In many ways, network monitoring and inference problems bear a strong resemblance to other "inverse problems" in which key aspects of a system are not directly observable. Familiar signal processing problems such as tomographic image reconstruction, system identification, and array processing all have interesting interpretations in the networking context. This article introduces the new field of network tomography, a field which we believe will benefit greatly from the wealth of signal processing theory and algorithms     

Modeling of program, erase and retention characteristics of charge-trap gate all around memories

This paper describes the effect of geometry in charge-trap (CT) memory devices. We first theoretically analyze the impact of the curvature radius on the behavior of the gate current in Gate-All-Around devices, and then describe the change to make to planar model in order to fit the cylindrical devices characteristics. This model is used to simulate Nanocrystal and SONOS program, erase and retention behaviors. The dynamics enhancement during program/erase due to the bending of the active region in such cylindrical devices is explained. The scaling perspectives conclude this paper.     

Scaling planar silicon devices

The generation-over-generation scaling of critical CMOS technology parameters is ultimately bound by nonscalable limitations, such as the thermal voltage and the elementary electronic charge. Sustained improvement in performance and density has required the introduction of new device structures and materials. Partially depleted SOI, a most recent MOSFET innovation, has extended VLSI performance while introducing unique idiosyncrasies. Fully depleted SOI is one logical extension of this device design direction. Gate dielectric tunneling, device self-heating, and single-event upsets present developers of these next-generation devices with new challenges. Strained silicon and high-permittivity gate dielectric are examples of new materials that will enable CMOS developers to continue to deliver device performance enhancements in the sub-100 nm regime.     

Joint Source–Channel Communication for Distributed Estimation in Sensor Networks

Power and bandwidth are scarce resources in dense wireless sensor networks and it is widely recognized that joint optimization of the operations of sensing, processing and communication can result in significant savings in the use of network resources. In this paper, a distributed joint source-channel communication architecture is proposed for energy-efficient estimation of sensor field data at a distant destination and the corresponding relationships between power, distortion, and latency are analyzed as a function of number of sensor nodes. The approach is applicable to a broad class of sensed signal fields and is based on distributed computation of appropriately chosen projections of sensor data at the destination - phase-coherent transmissions from the sensor nodes enable exploitation of the distributed beamforming gain for energy efficiency. Random projections are used when little or no prior knowledge is available about the signal field. Distinct features of the proposed scheme include: (1) processing and communication are combined into one distributed projection operation; (2) it virtually eliminates the need for in-network processing and communication; (3) given sufficient prior knowledge about the sensed data, consistent estimation is possible with increasing sensor density even with vanishing total network power; and (4) consistent signal estimation is possible with power and latency requirements growing at most sublinearly with the number of sensor nodes even when little or no prior knowledge about the sensed data is assumed at the sensor nodes.     

Extension and source/drain design for high-performance FinFET devices

Double gate devices based upon the FinFET architecture are fabricated, with gate lengths as small as 30 nm. Particular attention is given to minimizing the parasitic series resistance. Angled extension implants and selective silicon epitaxy are investigated as methods for minimizing parasitic resistance in FinFETs. Using these two techniques high performance devices are fabricated with on-currents comparable to fully optimized bulk silicon technologies. The influence of fin thickness on device resistance and short channel effects is discussed in detail. Devices are fabricated with fins oriented in the <100> and <100> directions showing different transport properties.     

A parallel algorithm evaluating the reliability of a system with known minimal cuts (paths)

A system with known minimal cuts is considered. In order to compute its reliability a binary tree is constructed with nodes being assigned numerical values. The value of each non-leaf node is a linear combination of its child nodes' values. The values of leaf nodes can be computed in a very simple way. The value of the root node is the system's reliability. The presented method is a memory saving one. Moreover, it is possible to apply parallel computation to the nodes located on the same level, which may significantly reduce the computing time.