Nonlinear Eulerian Analysis of Harmonic Generation in Traveling-Wave Tubes

A third-order nonlinear Eulerian hydrodynamic formulation was developed for the analysis of harmonic generation in helix traveling-wave tubes. The analysis was simple and computationally fast compared to Lagrangian analysis, and contrary to the existing belief, the theory could as well demonstrate the saturation behavior of the device. The performance of the theory was also found to be in close agreement with that of the Lagrangian analysis. The theory is expected to be useful as a first-hand design and simulation tool for microwave and millimetric wave traveling-wave tubes.     

Plastic Flow and Dislocation Compensation in ZnS y Se1?y /GaAs (001) Heterostructures

An important goal of lattice-mismatched semiconductor device design is control of threading dislocation densities, which are of particular importance for optoelectronic devices such as photodetectors and light-emitting diodes. The basis for this field of research is an understanding of the dislocation dynamics in mismatched heteroepitaxial structures. We have developed a dislocation dynamics model including dislocation multiplication, misfit–threading dislocation interactions, annihilation and coalescence, and thermal strain, which can be used to understand the strain relaxation and threading dislocation densities in arbitrarily graded ZnS _y Se_1?y /GaAs (001) structures. On the basis of this model, we demonstrate that the dislocation compensation mechanism, whereby mobile threading dislocations can be removed by insertion of a mismatched interface in a graded structure, can be explained by the bending over of threading dislocations associated with misfit segments of one sense by misfit dislocations having the opposite sense. Dislocation compensation, if utilized in device structures, can provide a pathway for the attainment of devices with low threading dislocation densities (D?<?10⁶?cm^?2) while using the minimum total thickness of epitaxial material, with a reduction in deposition time and source chemicals.     

Nonvolatile Memory Effect in Indium Gallium Arsenide-Based Metal–Oxide–Semiconductor Devices Using II–VI Tunnel Insulators

This paper reports the successful use of ZnSe/ZnS/ZnMgS/ZnS/ZnSe as a gate insulator stack for an InGaAs-based metal–oxide–semiconductor (MOS) device, and demonstrates the threshold voltage shift required in nonvolatile memory devices using a floating gate quantum dot layer. An InGaAs-based nonvolatile memory MOS device was fabricated using a high-κ II–VI tunnel insulator stack and self-assembled GeO _x -cladded Ge quantum dots as the charge storage units. A Si₃N₄ layer was used as the control gate insulator. Capacitance–voltage data showed that, after applying a positive voltage to the gate of a MOS device, charges were being stored in the quantum dots. This was shown by the shift in the flat-band/threshold voltage, simulating the write process of a nonvolatile memory device.     

Novel Multistate Quantum Dot Gate FETs Using SiO2 and Lattice-Matched ZnS-ZnMgS-ZnS as Gate Insulators

Multistate behavior has been achieved in quantum dot gate field-effect transistor (QDGFET) configurations using either SiO _x -cladded Si or GeO _x -cladded Ge quantum dots (QDs) with asymmetric dot sizes. An alternative method is to use both SiO _x -cladded Si and GeO _x -cladded Ge QDs in QDGFETs. In this paper, we present experimental verification of four-state behavior observed in a QDGFET with cladded Si and Ge dots site-specifically self-assembled in the gate region over a thin SiO₂ tunnel layer on a Si substrate. This paper also investigates the use of lattice-matched high-κ ZnS-ZnMgS-ZnS layers as a gate insulator in mixed-dot Si QDGFETs. Quantum-mechanical simulation of the transfer characteristic (I _D–V _G) shows four-state behavior with two intermediate states between the conventional ON and OFF states.     

Critical Layer Thickness in Exponentially Graded Heteroepitaxial Layers

Exponentially graded semiconductor layers are of interest for use as buffers in heteroepitaxial devices because of their tapered dislocation density and strain profiles. Here we have calculated the critical layer thickness for the onset of lattice relaxation in exponentially graded In _x Ga_1?x As/GaAs (001) heteroepitaxial layers. Upwardly convex grading with \( x = x_{\infty } \left( {1 - {\rm e}^{ - \gamma /y} } \right) \) was considered, where y is the distance from the GaAs interface, γ is a grading length constant, and x _∞ is the limiting mole fraction of In. For these structures the critical layer thickness was determined by an energy-minimization approach and also by consideration of force balance on grown-in dislocations. The force balance calculations underestimate the critical layer thickness unless one accounts for the fact that the first misfit dislocations are introduced at a finite distance above the interface. The critical layer thickness determined by energy minimization, or by a detailed force balance model, is approximately \( h_{\rm{c}} \approx <Exponentially graded semiconductor layers are of interest for use as buffers in heteroepitaxial devices because of their tapered dislocation density and strain profiles. Here we have calculated the critical layer thickness for the onset of lattice relaxation in exponentially graded In _x Ga_1−x As/GaAs (001) heteroepitaxial layers. Upwardly convex grading with x = x_￥ ( 1 - e ^{- g/y} ) x = x_{\infty } \left( {1 - {\rm e}^{ - \gamma /y} } \right) was considered, where y is the distance from the GaAs interface, γ is a grading length constant, and x _∞ is the limiting mole fraction of In. For these structures the critical layer thickness was determined by an energy-minimization approach and also by consideration of force balance on grown-in dislocations. The force balance calculations underestimate the critical layer thickness unless one accounts for the fact that the first misfit dislocations are introduced at a finite distance above the interface. The critical layer thickness determined by energy minimization, or by a detailed force balance model, is approximately h_c ? < h_{\rm{c}} \approx < Although these results were developed for exponentially graded In _x Ga_1−x As/GaAs (001), they may be generalized to other material systems for application to the design of exponentially graded buffer layers in metamorphic device structures such as modulation-doped field-effect transistors and light-emitting diodes.     

INSPAD: a system for automatic bond pad inspection

A method of detecting probe mark defects in semiconductor bond pads is presented that uses digitized images of color Polaroid photographs from an optical microscope. INSPAD inspects the bond pads in a magnified IC circuit image taken after the electrical testing stage. These are: probe marks must not extend beyond pad boundaries such that they damage glassivation; scratches on the bond pads must not exceed 50% of the bond pad width; and the probe marks must not exceed 25% of the bond pad area. Three types of commonly used bond pad geometries have been addressed. Morphological filtering is performed on the bond pad, to isolate and identify the major probe mark regions. Inspection of each pad takes approximately 2 to 3 s on an Apollo DN-4000 workstation which makes it suitable for real-time applications     

A 44 GHz monolithic semiconductor dipole antenna

Monolithic semiconductor antennas integrated with a diode detector have been fabricated using silicon-on-sapphire technology. The performance of these antennas is analyzed on the basis of earlier theoretical work on imperfectly conducting/resistive cylindrical dipoles. The measured radiation patterns of semiconductor antennas are compared with those of the corresponding printed metal dipoles.     

Cross-Layer Energy Based Clustering Technique for Heterogeneous Wireless Sensor Networks

Wireless Personal Communications - Effect of combination of dual split ring resonator and electromagnetic bandgap structures over substrate integrated waveguide and half-mode substrate integrated...     

Engineering New Microvascular Networks On-Chip: Ingredients,Assembly, and Best Practices

Tissue engineered grafts show great potential as regenerative implants for diseased or injured tissues within the human body. However, these grafts suffer from poor nutrient perfusion and waste transport, thus decreasing their viability post-transplantation. Graft vascularization is therefore a major area of focus within tissue engineering because biologically relevant conduits for nutrient and oxygen perfusion can improve viability post-implantation. Many researchers used microphysiological systems as testing platforms for potential grafts owing to an ability to integrate vascular networks as well as biological characteristics such as fluid perfusion, 3D architecture, compartmentalization of tissue-specific materials, and biophysical and biochemical cues. Although many methods of vascularizing these systems exist, microvascular self-assembly has great potential for bench-to-clinic translation as it relies on naturally occurring physiological events. In this review, the past decade of literature is highlighted, and the most important and tunable components yielding a self-assembled vascular network on chip are critically discussed: endothelial cell source, tissue-specific supporting cells, biomaterial scaffolds, biochemical cues, and biophysical forces. This paper discusses the bioengineered systems of angiogenesis, vasculogenesis, and lymphangiogenesis and includes a brief overview of multicellular systems. It concludes with future avenues of research to guide the next generation of vascularized microfluidic models.