Microstructure-Mechanical Property Relationships in Hot Isostatically Pressed Alumina and Zirconia-Toughened Alumina

The rates of densification and the mechanical properties of pure Al₂O₃ and ZrO₂-toughened Al₂O₃ (ZTA) have been investigated as a function of the temperatures and time schedules used for hot isostatic pressing (HIP) as a postsintering heat treatment for samples which had already been pressureless sintered in air at 1460°C for 45 min. ZTA hot isostatically presed at 1400°C had a finer grain size and a narrower grain size distribution than ZTA hot isostatically pressed at 1600°C. At both HIP conditions, the density which could be obtained was almost the maximum theoretical density. The amount of grinding-induced and fracture-induced monoclinic ZrO₂ formed as a result of the tetragonal → monoclinic martensitic transformation in ZTA was higher in the samples hot isostatically pressed at 1400°C. ZTA hot isostatically pressed at 1600°C and 100 MPa had fewer flaws and higher strengths than ZTA hot isostatically pressed at 1400°C for the same time, with a gradual improvement in mechanical properties with increasing HIP time at each of these two temperatures. The best mechanical properties were obtained from ZTA hot isostatically pressed at 100 MPa and 1600°C for 1 h: these specimens had a four-point bend strength of 940 ± 15 MPa at room temperature and 540 ± 15 MPa at 1000°C and an indentation fracture toughness at room temperature of 9.4 ± 0.2 MPa·m^1/2.     

Hybrid ring coupler for W-band MMIC applications using MEMS technology

The hybrid ring coupler was designed and fabricated on a GaAs substrate using surface micromachining techniques, which adopted dielectric-supported air-gapped microstrip line (DAML) structure. The fabrication process of DAML is compatible with the standard monolithic microwave integrated circuit (MMIC) techniques, and the hybrid ring coupler can be simply integrated into a plane-structural MMIC. The fabricated hybrid ring coupler shows wideband characteristics of the coupling loss of 3.57 /spl plusmn/ 0.22dB and the transmission loss of 3.80 /spl plusmn/ 0.08dB across the measured frequency range of 85 to 105GHz. The isolation characteristics and output phase differences are -34dB and 180/spl plusmn/1/spl deg/, at 94GHz, respectively.     

The Effect of Gate‐Dielectric Surface Energy on Pentacene Morphology and Organic Field‐Effect Transistor Characteristics

The effects of the surface energy of polymer gate dielectrics on pentacene morphology and the electrical properties of pentacene field‐effect transistors (FETs) are reported, using surface‐energy‐controllable poly(imide‐siloxane)s as gate‐dielectric layers. The surface energy of gate dielectrics strongly influences the pentacene film morphology and growth mode, producing Stranski–Krastanov growth with large and dendritic grains at high surface energy and three‐dimensional island growth with small grains at low surface energy. In spite of the small grain size (≈ 300 nm) and decreased ordering of pentacene molecules vertical to the gate dielectric with low surface energy, the mobility of FETs with a low‐surface‐energy gate dielectric is larger by a factor of about five, compared to their high‐surface‐energy counterparts. In pentacene growth on the low‐surface‐energy gate dielectric, interconnection between grains is observed and gradual lateral growth of grains causes the vacant space between grains to be filled. Hence, the higher mobility of the FETs with low‐surface‐energy gate dielectrics can be achieved by interconnection and tight packing between pentacene grains. On the other hand, the high‐surface‐energy dielectric forms the first pentacene layer with some voids and then successive, incomplete layers over the first, which can limit the transport of charge carriers and cause lower carrier mobility, in spite of the formation of large grains (≈ 1.3 μm) in a thicker pentacene film.     

A Power-Efficient High-Throughput 32-Thread SPARC Processor

This first generation of "Niagara" SPARC processors implements a power-efficient Chip Multi-Threading (CMT) architecture which maximizes overall throughput performance for commercial workloads. The target performance is achieved by exploiting high bandwidth rather than high frequency, thereby reducing hardware complexity and power. The UltraSPARC T1 processor combines eight four-threaded 64-b cores, a floating-point unit, a high-bandwidth interconnect crossbar, a shared 3-MB L2 Cache, four DDR2 DRAM interfaces, and a system interface unit. Power and thermal monitoring techniques further enhance CMT performance benefits, increasing overall chip reliability. The 378-mm² die is fabricated in Texas Instrument's 90-nm CMOS technology with nine layers of copper interconnect. The chip contains 279 million transistors and consumes a maximum of 63 W at 1.2 GHz and 1.2 V. Key functional units employ special circuit techniques to provide the high bandwidth required by a CMT architecture while optimizing power and silicon area. These include a highly integrated integer register file, a high-bandwidth interconnect crossbar, the shared L2 cache, and the IO subsystem. Key aspects of the physical design methodology are also discussed     

Resistive switching characteristics of ultra-thin TiOx

We investigated the resistive switching characteristics of Ir/TiO_x/TiN structure with 50 nm active area. We successfully formed ultra-thin (4 nm) TiO_x active layer using oxidation process of TiN BE, which was confirmed by X-ray Photoelectron Spectroscopy (XPS) depth profiling. Compared to large area device (50 μm), which shows only ohmic behavior, 250 and 50 nm devices show very stable resistive switching characteristics. Due to the formation and rupture of oxygen vacancies induced conductive filament at Ir and TiO_x interface, bipolar resistive switching was occurred. We obtained excellent switching endurance up to 10⁶ times with 100 ns pulse and negligible degradation of each resistance state at 85 °C up to 10⁴ s.     

Improvement of the cell performance in the ZnS/Cu(In,Ga)Se2 solar cells by the sputter deposition of a bilayer ZnO : Al film

ZnS is a candidate to replace CdS as the buffer layer in Cu(In,Ga)Se₂ (CIGS) solar cells for Cd‐free commercial product. However, the resistance of ZnS is too large, and the photoconductivity is too small. Therefore, the thickness of the ZnS should be as thin as possible. However, a CIGS solar cell with a very thin ZnS buffer layer is vulnerable to the sputtering power of the ZnO : Al window layer deposition because of plasma damage. To improve the efficiency of CIGS solar cells with a chemical‐bath‐deposited ZnS buffer layer, the effect of the plasma damage by the sputter deposition of the ZnO : Al window layer should be understood. We have found that the efficiency of a CIGS solar cell consistently decreases with an increase in the sputtering power for the ZnO : Al window layer deposition onto the ZnS buffer layer because of plasma damage. To protect the ZnS/CIGS interface, a bilayer ZnO : Al film was developed. It consists of a 50‐nm‐thick ZnO : Al plasma protection layer deposited at a sputtering power of 50 W and a 100‐nm‐thick ZnO : Al conducting layer deposited at a sputtering power of 200 W. The introduction of a 50‐nm‐thick ZnO : Al layer deposited at 50 W prevented plasma damage by sputtering, resulting in a high open‐circuit voltage, a large fill factor, and shunt resistance. The ZnS/CIGS solar cell with the bilayer ZnO : Al film yielded a cell efficiency of 14.68%. Therefore, the application of bilayer ZnO : Al film to the window layer is suitable for CIGS solar cells with a ZnS buffer layer. Copyright © 2012 John Wiley & Sons, Ltd.     

Thermal Resistance Measurement of LED Package with Multichips

Thermal transient measurements of high power GaN-based light-emitting diodes (LEDs) with multichip designs are presented and discussed in the paper. Once transient cooling curve was obtained, the structure function theory was applied to determine the thermal resistance of packages. The total thermal resistance from junction to ambient considering optical power is 19.87 K/W, 10.78 K/W, 6.77 K/W for the one-chip, two-chip and four-chip packages, respectively. The contribution of each component to the total thermal resistance of the package can be determined from the cumulative structure function and differential structure function. The total thermal resistance of multichip packages is found to decrease with the number of chips due to parallel heat dissipation. However, the effect of the number of chips on thermal resistance of package strongly depends on the ratio of partial thermal resistance of chip and that of slug. Therefore, an important thermal design rule for packaging of high power multichip LEDs has been analogized.     

Strain‐Visualization with Ultrasensitive Nanoscale Crack‐Based Sensor Assembled with Hierarchical Thermochromic Membrane

As eidetic signal recognition has become important, displaying mechanical signals visually has imposed huge demands for simple readability and without complex signal processing. Such visualization of mechanical signals is used in delicate urgent medical or safety‐related industries. Accordingly, chromic materials are considered to facilitate visualization with multiple colors and simple process. However, the response and recovery time is very long, such that rapid regular signals are unable to be detected, i.e., physiological signals, such as respiration. Here, the simple visualization of low strain ≈2%, with ultrasensitive crack‐based strain sensors with a hierarchical thermochromic layer is suggested. The sensor shows a gradient color change from red to white color in each strain, which is attributed to the hierarchical property, and the thermal response (recovery) time is dramatically minimized within 0.6 s from 45 to 37 °C, as the hierarchical membrane is inspired by termite mounds for efficient thermal management. The fast recovery property can be taken advantage of in medical fields, such as monitoring regular respiration, and the color changes can be delicately monitored with high accuracy by software on a mobile phone.