信道预测对自适应调制系统性能的影响分析

自适应调制系统通常根据当前信道条件调整未来的调制和编码方式来提高频谱效率,存在的问题是信道的不断变化使得这样的调整不准确,反而导致性能恶化.本文主要研究了信道变化对自适应调制系统性能的影响,调整方式有以下两种:使用当前信道估计值来判断下一帧调制方式;采用MMSE信道预测算法对下一帧信道值进行预测,再根据预测值判断调制方式.同时推导出两种情况下正确选择调制方式的概率公式.数值结果表明以当前值代替未来值的准确程度是和多普勒与帧长的乘积成反比的,且和平均信噪比距离信噪比界值的程度相关,而信道预测时选择调制方式的正确概率和多普勒与帧长的乘积也成反比,且和预测采用的阶次成反比.     

基于VMM的外部存储接口模块的验证平台搭建

本文首先介绍了VMM层次化验证方法学的基本思想和方法,将其与传统的芯片验证技术进行了对比,并进一步对基于VMM(Verification Methodology Manual For System Verilog)方法学的验证平台结构和各个组成模块进行了详细的介绍。最后以外部存储接口(EMI)模块为例对VMM验证平台的搭建进行了具体说明,并给出了验证结果。     

扩展目标幸运成像技术的理论和实验研究

地基望远镜的成像分辨率通常都受到大气湍流的限制,这种限制在对扩展目标进行观测成像时变得尤为显著。幸运成像技术是一种基于目标序列短曝光图像选取、配准、叠加的事后图像处理方法,能够有效降低大气湍流导致的成像闪烁和抖动对图像质量的影响,提高望远镜的成像分辨率。介绍了扩展目标幸运成像技术的基本原理和基本流程,并应用该项技术对近地扩展目标大气湍流成像的实验观测数据进行事后处理。处理结果表明,幸运成像技术能够提高扩展目标通过湍流大气的成像分辨率。     

无Cr腐蚀液显示直拉Si单晶中的氧化诱生层错

Si抛光片的氧化诱生层错(OSF)是一种重要的工艺诱生缺陷,为提高Si抛光片质量,应对氧化诱生层错的产生有充分的认识和了解,并加以克服,而简单、快捷、准确地显示缺陷是首要条件.介绍了采用环保的无Cr腐蚀液显示氧化诱生层错,实验发现无Cr腐蚀液能很好地显示氧化诱生层错,比较了无Cr腐蚀液和其他常用腐蚀液的缺陷腐蚀形貌,探讨了无Cr腐蚀液的腐蚀机理及腐蚀条件.实验发现环保的无Cr腐蚀液能很好地显示直拉Si单晶中的氧化诱生层错,能应用于生产.     

基于DSP和CPLD的脉冲氙灯电流实时采集系统的研制

介绍了基于DSP（数字信号处理器）和CPLD（复杂可编程逻辑器件）为控制核心、MAX125为A／D转换芯片的脉冲多路氙灯负载电流同步采集系统的研制,使用CPLD同时控制多片MAX125来实现了高速多路波形同步采集。详细介绍了波形采集模块的硬件及软件设计,重点分析了MAX125的控制时序和CPLD的控制逻辑。实验结果表明该装置完全能满足系统精度和实时性的要求,已经被成功应用到神光-Ⅲ主机激光装置验证系统的能源组件中,运行可靠、稳定。     

NFO/PZT复合磁电薄膜生长制备及性能的研究

采用脉冲激光沉积(PLD)法,在制备有SrRuO3底电极的SrTiO3(001)基片上生长高质量的NiFe2O4/Pb(Zr0.52Ti0.48)O3双层复合磁电薄膜.用X-射线衍射(XRD)对复合薄膜的微结构进行详细表征,结果表明,复合薄膜中NiFe2O4、Pb(Zr0.52Ti0.48)O3结晶良好,且具有单一的面外取向,Φ扫描模式显示NiFe2O4、Pb(Zr0.52Ti0.48)O3均延SrTiO3(001)方向外延生长.磁电性能表征结果表明,由于界面应力效应的作用,复合薄膜的铁电性较单层Pb(Zr0.52Ti0.48)O3明显减弱,而铁磁性基本保持NiFe2O4的软磁特性.     

Experimental and numerical analysis of BGA lead-free solder joint reliability under board-level drop impact

Board-level solder joint reliability is very critical for handheld electronic products during drop impact. In this study, board-level drop test and finite element method (FEM) are adopted to investigate failure modes and failure mechanisms of lead-free solder joint under drop impact. In order to make all ball grid array (BGA) packages on the same test board subject to the uniform stress and strain level during drop impact, a test board in round shape is designed to conduct drop tests. During these drop tests, the round printed circuit board assembly (PCBA) is suffered from a specified half-sine acceleration pulse. The dynamic responses of the PCBA under drop impact loading are measured by strain gauges and accelerometers. Locations of the failed solder joints and failure modes are examined by the dye penetration test and cross section test. While in simulation, FEM in ABAQUS software is used to study transient dynamic responses. The peeling stress which is considered as the dominant factor affecting the solder joint reliability is used to identify location of the failed solder joints. Simulation results show very good correlation with experiment measurement in terms of acceleration response and strain histories in actual drop test. Solder joint failure mechanisms are analyzed based on observation of cross section of packages and dye and pry as well. Crack occurred at intermetallic composite (IMC) interface on the package side with some brittle features. The position of maximum peeling stress in finite element analysis (FEA) coincides with the crack position in the cross section of a failed package, which validated our FEA. The analysis approach combining experiment with simulation is helpful to understand and improve solder joint reliability.     

Effects of periphery encapsulation material on the characteristics of micro vacuum dielectric capacitor

The effects of the periphery sealant on the electrical characteristics of vacuum dielectric capacitors (VDCs) are modeled. For the square shape VDCs, their characteristics are predominantly determined by the ratio of capacitor side length versus the width of boundary sealant layer, r. The smaller of the r value, the smaller of the dissipation factor, and the better frequency response of the VDCs are found. To achieve a dissipation factor of less than 10⁻⁵ at 1 GHz, the dimension parameter, r, should be smaller than 0.05 which has been achieved based on the present technology for a capacitor with size larger than 4 mm × 4 mm. The leakage current can also be reduced significantly in the VDCs. We found that the leakage current is mainly governed by the Poole-Frenkel emission of electrons over the periphery region. The present results have demonstrated that the VDC structure is a promising technology option for making high-frequency micro capacitors.     

Epitaxy and Characteristics of Resonant Cavity LEDs at 650 nm

Resonant-cavity light-emitting diodes (RCLED) at 650 nm wavelength were grown by metal organic chemical vapor deposition. In order to improve the interface quality and reduce the device voltage, an AlGaInP material system has been chosen to grow the top DBRs. The emission properties of the RCLED were characterized by measuring PL and EL spectra. The average emission power of the device is 0.5 mW at 20 mA and 2.2 V, and its spectrum full width at half maximum is about 10 nm.     

A low power high linearity baseband for a direct conversation CMMB tuner

An analog baseband circuit made in a 0.35-μm SiGe BiCMOS process is presented for China Multimedia Mobile Broadcasting (CMMB) direct conversion receivers. A high linearity 8th-order Chebyshev low pass filter (LPF) with accurate calibration system is used. Measurement results show that the filter provides 0.5-dB passband ripple, 4% bandwidth accuracy, and -35-dB attenuation at 6 MHz with a cutoff frequency of 4 MHz. The current steering type variable gain amplifier (VGA) achieves more than 40-dB gain range with excellent temperature compensation. This tuner baseband achieves an OIP3 of 25.5 dBm, dissipates 16.4 mA under a 2.8-V supply and occupies 1.1 mm2 of die size.