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991.
This system presents an energy harvesting system that generates bipolar output voltage (±1 V) based on a miniature 1:1 turn-ratio pulse transformer boost converter using sub-threshold level input voltage source. A shunt regulator is designed using six-transistor Schmitt-Trigger core to limit the boost converter output voltage. Another power stage, i.e. a fully integrated on-chip single-stage cross-coupled charge pump, then generates 3 V output from the unused extra output power of boost converter, which is shunted otherwise. The increased voltage headroom generated is instrumental for sensor, analog and RF circuits. Charge pump clock frequency is designed to adaptively tracking the input voltage, which is sensed using power-saving time-domain digital technique. Based on a standard CMOS 0.13-µm technology, chip measurement verified the operations of the boost converter, shunt regulator and bipolar charge pump prototypes, respectively. Simulations confirmed the full system operations. During start-up, the system only requires minimum start-up input voltage of 36 mV at input power of 5.8 µW. 相似文献
992.
Algebraic immunity quantified the resistance of a Boolean function to the algebraic attack.Recently,Mesnager,et al showed that there were direct linked between the annihilators used in algebraic attacks and the coding theory.They showed that the lower bound of the algebraic immunity of Boolean functions could been derived from the minimum distance of the associated cyclic codes.An open problem proposed by Mesnager is settled with a detailed proof.Also,a lower bound of algebraic immunity of a class of Boolean functions will be introduced. 相似文献
993.
针对传统的除垢方法不能在线除垢的问题,提出了一种具有在线除垢特点的超声波除垢器.本设计是以STC12C2052AD单片机为核心控制器,通过SG3525控制IGBT开关来驱动超声波振荡器以达到在线除垢;从控制超声波振荡系统的角度出发,对超声波发生器工作原理,硬件电路部分及软件部分进行了解释和分析.实验表明,除垢器完全可以达到在线除垢要求. 相似文献
994.
Constraints are commonly used in both simulation and formal verification in order to specify expected input conditions and
state transitions. Constraint solving is a process to determine input vectors which satisfy the set of constraints during constrained random simulation. Even though
constraints are used in formal property checking to restrict the search space, constraint solving has never had direct application
to formal property checking. There are often many simple, yet powerful, invariants that can be learned from constraint solving
during constrained random simulation. These invariants are shown in this paper to significantly simplify the formal verification
problem. We use approximate constraint solving to compute an approximate set of valid input vectors. The approximate set of
valid input vectors are a strict superset of the set of all legal input vectors. We use BDD techniques to compute these input
vectors during constrained random simulation, then process the resulting BDDs for learning invariants which can be used during
formal property checking. This paper presents efficient BDD algorithms to learn invariants from the BDDs generated from approximate
constraint solving. We also present how these learned invariants can be applied to the formal property checking. Experimental
results show that invariants learned during constraint solving can significantly improve the performance of formal property
checking with many industrial designs. 相似文献
995.
996.
Based on the surface impedance theory (SIT) and the coupled-wave theory (CWT), this paper has established the second-order
transmission line equation applicable to coaxial resonators with corrugated inner conductor. By utilizing the equation, the
resonant frequency, Q factor and field profiles geometry of the eigenmodes of coaxial resonators can be calculated in view
of the mode coupling, and the variables of the slot width and depth in the coupling coefficient can also be applied to calculate
their impact on the resonant frequency and Q factor. The numerical results show that, the slot width and depth have significant
impact on the resonant frequency, but their effect on Q factor is approximately negligible. 相似文献
997.
Shi-Chang Zhang 《Journal of Infrared, Millimeter and Terahertz Waves》2010,31(3):249-258
A planar electrostatic wiggler is formed by two parallel metallic plates, where the upper-plate is corrugated with sinusoidal
ripples and connected to a negative voltage and the lower-plate is smooth and grounded. The field distribution is mathematically
derived in detail. It is demonstrated that this planar electrostatic wiggler can efficiently modulate the motion of relativistic
electrons just as a magneto-static wiggler does in a free-electron laser. Results obtained here will provide basis to analyze
the amplification mechanism of a fast wave by a relativistic electron beam in a planar electrostatic wiggler. 相似文献
998.
Error concealment techniques are widely used as efficient ways to recover the lost information at the decoder. This paper
proposes an adaptive pixel interpolation technique for spatial error concealment in the block based coding system. For a missing
pixel in a corrupted block, its value is derived from four neighborhoods of the block through interpolation using multiple
prediction strategy. The weighting rules of these four neighborhood blocks are carefully designed with regard to three factors,
the distance to the missing pixels within the given corrupted block, the percentage of uncorrupted pixels, and the similarity
to the given corrupted block. The proposed method works effectively in consecutive block loss situation, which is common in
real applications of video transmission. Experimental results show the proposed technique gains more accurate recovery of
the missing pixels than the existing schemes. 相似文献
999.
1000.
Mohamed Al-Azab 《Analog Integrated Circuits and Signal Processing》2010,65(2):335-339
This paper describes a 5.2 GHz voltage-controlled oscillator (VCO) as a key component in RF transceivers. The circuit includes
a complementary cross-coupled MOSFET as a negative conductance, beside a tank circuit which consists of an optimal on-chip
spiral inductor (L), and an accumulation mode MOS varactor (C(V)). A model for phase noise and figure merit is introduced
and verified through simulation in a standard 0.13 μm CMOS process. The VCO core drew a 4.2 mA of current from a 1.2 V power
supply and a phase noise of −98.5 dBc/Hz at 1 MHz offset from the 5.2 GHz carrier was calculated. The whole performance of
the circuit specifically the tuning range was found to be 26%. 相似文献